View W742E_52414.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

W742E/C811 4-BIT MICROCONTROLLER
Table of Contents1. 2. 3. 4. 5. GENERAL DESCRIPTION .............................................................................................................3 FEATURES.....................................................................................................................................3 PIN CONFIGURATION...................................................................................................................5 3.1 W742C811 PAD List .........................................................................................................6 PIN DESCRIPTION ........................................................................................................................9 FUNCTIONAL DESCRIPTION .....................................................................................................11 5.1 5.2 5.3 Program Counter (PC) ....................................................................................................11 Stack Register (STACK)..................................................................................................11 Program Memory (ROM).................................................................................................12
5.3.1 5.3.2 ROM Page Register (ROMPR) .........................................................................................13 ROM Addressing Mode ....................................................................................................13 Architecture ......................................................................................................................15 RAM Page Register (PAGE).............................................................................................15 WR Page Register (WRP)................................................................................................16 Data Bank Register (DBKRH, DBKRL).............................................................................17 RAM Addressing Mode.....................................................................................................18
5.4
Data Memory (RAM)........................................................................................................15
5.4.1 5.4.2 5.4.3 5.4.4 5.4.5
5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12
Accumulator (ACC) .........................................................................................................19 Arithmetic and Logic Unit (ALU) ......................................................................................19 Main Oscillator.................................................................................................................19 Sub-oscillator...................................................................................................................20 Dividers............................................................................................................................20 Dual-clock Operation .......................................................................................................20 Watchdog Timer (WDT) ..................................................................................................21 Timer/Counter .................................................................................................................22
5.12.1 5.12.2 Timer 0 (TM0) .................................................................................................................22 Timer 1 (TM1) .................................................................................................................23 Mode Register 1 (MR1) ..................................................................................................25
5.13 5.14 5.15 5.16
Mode Register 0 (MR0) ...................................................................................................25
5.13.1
Interrupts .........................................................................................................................25 Stop Mode Operation ......................................................................................................27
5.15.1 Stop Mode Wake-up Enable Flag for RC and RD Port (SEF) ........................................27
Hold Mode Operation ......................................................................................................27 Publication Release Date: December 2000 Revision A1
-1-
W742E/C811
5.16.1 5.16.2 5.16.3 5.16.4 5.16.5 Hold Mode Release Enable Flag (HEF, HEFD)..............................................................29 Interrupt Enable Flag (IEF) .............................................................................................29 Port Enable Flag (PEF, P1EF)........................................................................................30 Hold Mode Release Condition Flag (HCF, HCFD) .........................................................30 Event Flag (EVF,EVFD)..................................................................................................31
5.17 5.18
Reset Function ................................................................................................................32 Input/Output Ports RA, RB & P0......................................................................................32
5.18.1 5.18.2 5.18.3 5.18.4 5.18.5 Port Mode 0 Register (PM0) ...........................................................................................33 Port Mode 1 Register (PM1) ...........................................................................................34 Port Mode 2 Register (PM2) ...........................................................................................34 Port Mode 6 Register (PM6) ...........................................................................................34 Serial I/O Interface..........................................................................................................35 Port Status Register 0 (PSR0)........................................................................................39 Port Status Register 1 (PSR1)........................................................................................40
5.19 5.20 5.21 5.22 5.23
Input Ports RC .................................................................................................................37
5.19.1 5.20.1
Input Ports RD .................................................................................................................39 Output Port RE & RF .......................................................................................................41 Input Port P1....................................................................................................................41 DTMF Output Pin (DTMF) ...............................................................................................41
5.23.1 5.23.2 DTMF register.................................................................................................................42 Dual Tone Control Register (DTCR) ...............................................................................42
5.24 5.25
MFP Output Pin (MFP) ....................................................................................................42 LCD Controller/Driver ......................................................................................................44
5.25.1 5.25.2 5.25.3 5.25.4 LCD RAM addressing method ........................................................................................45 LCD voltage and contrast adjusting................................................................................46 SEG32-SEG39 using as DC output (NMOS open drain type) ........................................47 The output waveforms for the LCD driving mode ...........................................................47
6. 7. 8. 9. 10.
ABSOLUTE MAXIMUM RATINGS ...............................................................................................48 DC CHARACTERISTICS..............................................................................................................48 AC CHARACTERISTICS..............................................................................................................49 INSTRUCTION SET TABLE.........................................................................................................50 PACKAGE DIMENSIONS .............................................................................................................59
-2-
W742E/C811
1. GENERAL DESCRIPTION
The W742E/C811 (W742C811 is mask type, W742E811 is electrical erasable EPROM type) is a highperformance 4-bit microcontroller (C) that built in 640-dot LCD driver. The device contains a 4-bit ALU, two 8-bit timers, two dividers in dual-clock operation, a 40 x 16 LCD driver, ten 4-bit I/O ports (including 2 output port for LED driving), multiple frequency output, and one channel DTMF generator. There are also eleven interrupt sources and 16-level stack buffer. The W742E/C811 operates on very low current and has three power reduction modes, hold mode, stop mode and slow mode, which help to minimize power dissipation.
2. FEATURES
*
Operating Voltage - 2.4V - 5.5V for mask type - 2.4V - 4.8V for electrical erasable EPROM type
* *
Dual-clock Operation Main Oscillator - 3.58 MHz or 400 KHz can be selected by code option - Crystal or RC oscillator can be selected by code option
* *
Sub-oscillator - Connect to 32.768 KHz crystal only Memory - 16384(16K) x 16 bit program ROM (including 64K x 4 bit look-up table) - 5120(5K) x 4 bit data RAM (including 16 nibbles x 16 pages working registers) - 40 x 16 LCD data RAM
*
40 Input/Output Pins - Port for input only: 3 ports/12 pins - Input/output ports: 3 ports/12 pins - High sink current output port for LED driving: 2 port /8 pins - DC output port: 2 ports/ 8 pins (selected by code option)
*
Power-down Mode - Hold mode: no operation (main oscillator and sub-oscillator still operate) - Stop mode: no operation (main oscillator and sub-oscillator are stopped) - Slow mode: main oscillator is stopped, system is operated by the sub-oscillator (32.768 KHz)
-3-
Publication Release Date: December 2000 Revision A1
W742E/C811
*
Eleven Interrupt Sources - Four internal interrupts (Divider0, Divider1, Timer 0, Timer 1) - Seven external interrupts (RC.0-3, P1.2 ( INT0 ), Serial Port, P1.3 ( INT1 ))
*
LCD Driver Output - 40 segments x 16 commons - 1/8 or 1/16 duty (selected by code option) 1/5 bias driving mode - Clock source should be the sub-oscillator clock in the dual-clock operation mode - 8 level software LCD contrast adjusting - LCD operating voltage source could come from VDD or VLCD1 pin input
*
MFP Output Pin - Output is software controlled to generate modulating or nonmodulating frequency - Works as frequency output specified by Timer 1 - Key tone generator
* * *
DTMF Output pin - Output is one channel Dual Tone Multi-Frequency signal for dialling 8-bit Serial I/O Interface - 8-bit transmit/receive mode by internal or external clock source Two Built-in 14-bit Frequency Dividers - Divider0: the clock source is the main oscillator (Fosc) - Divider1: the clock source is the sub-oscillator (Fs)
*
Two Built-in 8-bit Programmable Countdown Tmers - Timer 0: one of two internal clock frequencies (FOSC/4 or FOSC/1024) can be selected - Timer 1: with auto-reload function and one of two internal clock frequencies (FOSC or FOSC/64 or Fs) can be selected (signal output through MFP pin)
* * * *
Built-in 18/15-bit Watchdog Timer Selectable for System Reset, Enable/Disable by Code Option Powerful Instruction Set 16-level Stack Buffer Packaged in 100-pin QFP
-4-
W742E/C811
3. PIN CONFIGURATION
S E G 3 0
S E G 2 9
S E G 2 8
S E G 2 7
S E G 2 6
S E G 2 5
SS EE GG 22 43
S E G 2 2
SSS EEE GGG 221 109
S E G 1 8
S E G 1 7
SS EE GG 11 65
S E G 1 4
S E G 1 3
SS EE GG 11 21
SEG31 (K0.0) S E G 3 2 (K0.1) S E G 3 3 (K0.2) S E G 3 4 (K0.3) S E G 3 5 (K1.0) S E G 3 6 (K1.1) S E G 3 7 (K1.2) S E G 3 8 (K1.3) S E G 3 9 COM08 COM09 COM10 COM11 COM12 COM13 COM14 COM15 RA0 RA1 RA2 [Data_IO] RA3 RB0 RB1 RB2 RB3 MFP DTMF XOUT2 XIN2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1 0 0
9 9
9 8
9 7
9 6
9 5
9 4
9 3
9 2
9 1
9 0
8 9
8 8
8 7
8 6
8 5
8 4
8 3
8 2
8 1 80 79 78 77 76 75 74 73 72 71 70 69 68
SEG10 SEG09 SEG08 SEG07 SEG06 SEG05 SEG04 SEG03 SEG02 SEG01 SEG00 COM00 COM01 COM02 COM03 COM04 COM05 COM06 COM07 VLCD1 CP CN P13 P12 P11 P10 P03 P02 P01 P00 [mode]
W742E/C811
100-pin QFP
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
3 9
4 0
44 12
4 3
4 4
4 5
444 678
4 9
5 0
X I N 1
XR OC U0 T 1
R C 1
R C 2
RRR CDD 301
R D 2
R D 3
R E 0
R E 1
R E 2
R E 3
R F 0
R F 1
R F 2
R F 3
/V RD ED S E T [Vpp]
-5-
Publication Release Date: December 2000 Revision A1
W742E/C811
3.1 W742C811 PAD List
** Shrink factor: 1.000000 ** Window: (xl = -1635.00, yl = -2140.00), (xh = 1635.00, yh = 2140.00) ** Windows size: width = 3270.00, length = 4280.00 ============================================================================== PAD NO PAD NAME PIN NAME X Y ============================================================================== 1 SEG<31> 1 -1530.00 1970.48 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 SEG<32> SEG<33> SEG<34> SEG<35> SEG<36> SEG<37> SEG<38> SEG<39> COM<8> COM<9> COM<10> COM<11> COM<12> COM<13> COM<14> COM<15> RA0 RA1 RA2 RA3 RB0 RB1 RB2 RB3 MFP DTMF 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 -1530.00 -1530.00 -1530.00 -1530.00 -1530.00 -1530.00 -1530.00 -1530.00 -1530.00 -1530.00 -1530.00 -1530.00 -1530.00 -1530.00 -1530.00 -1530.00 -1530.00 -1530.00 -1530.00 -1530.00 -1530.00 -1530.00 -1530.00 -1530.00 -1530.00 -1530.00 1840.48 1710.48 1580.48 1450.48 1320.48 1190.48 1060.48 930.48 800.48 670.48 540.48 410.48 280.48 150.48 20.48 -109.53 -233.53 -357.53 -481.53 -605.53 -729.53 -853.53 -977.53 -1101.53 -1225.53 -1349.53
28 XOUT2 28 -1530.00 -1473.53 ============================================================================== -6-
W742E/C811
W742C811 PAD List, continued
============================================================================== PAD NO PAD NAME PIN NAME X Y ============================================================================== 29 XIN2 29 -1530.00 -1603.53 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 VSS XIN1 XOUT1 RC0 RC1 RC2 RC3 RD0 RD1 RD2 RD3 RE0 RE1 RE2 RE3 RF0 RF1 RF2 RF3 RES VDD P00 P01 P02 P03 P10 P11 P12 P13 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 -1530.00 -1227.75 -1097.75 -967.75 -837.75 -707.75 -577.75 -447.75 -317.75 -187.75 -57.75 72.25 202.25 332.25 462.25 592.25 722.25 852.25 982.25 1112.25 1242.25 1527.33 1527.33 1527.33 1527.33 1527.33 1527.33 1527.33 1527.33 -1733.53 -2035.00 -2035.00 -2035.00 -2035.00 -2035.00 -2035.00 -2035.00 -2035.00 -2035.00 -2035.00 -2035.00 -2035.00 -2035.00 -2035.00 -2035.00 -2035.00 -2035.00 -2035.00 -2035.00 -2035.00 -1733.53 -1603.53 -1473.53 -1349.53 -1225.53 -1101.53 -977.53 -853.53
59 CN 59 1527.33 -729.53 ==============================================================================
-7-
Publication Release Date: December 2000 Revision A1
W742E/C811
W742C811 PAD List, continued
============================================================================== PAD NO PAD NAME PIN NAME X Y ============================================================================== 60 CP 60 1527.33 -605.53 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 VLCD1 COM<7> COM<6> COM<5> COM<4> COM<3> COM<2> COM<1> COM<0> SEG<0> SEG<1> SEG<2> SEG<3> SEG<4> SEG<5> SEG<6> SEG<7> SEG<8> SEG<9> SEG<10> SEG<11> SEG<12> SEG<13> SEG<14> SEG<15> SEG<16> SEG<17> SEG<18> SEG<19> 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 1527.33 1527.33 1527.33 1527.33 1527.33 1527.33 1527.33 1527.33 1527.33 1527.33 1527.33 1527.33 1527.33 1527.33 1527.33 1527.33 1527.33 1527.33 1527.33 1527.33 1242.25 1112.25 982.25 852.25 722.25 592.25 462.25 332.25 202.25 -481.53 -354.53 -224.53 -94.53 35.48 165.48 295.48 425.48 555.48 685.48 815.48 945.48 1075.48 1205.48 1335.48 1465.48 1595.48 1725.48 1855.48 1985.48 2019.15 2019.15 2019.15 2019.15 2019.15 2019.15 2019.15 2019.15 2019.15
90 SEG<20> 90 72.25 2019.15 ==============================================================================
-8-
W742E/C811
W742C811 PAD List, continued
============================================================================== PAD NO PAD NAME PIN NAME X Y ============================================================================== 91 SEG<21> 91 -57.75 2019.15 92 93 94 95 96 97 98 99 SEG<22> SEG<23> SEG<24> SEG<25> SEG<26> SEG<27> SEG<28> SEG<29> 92 93 94 95 96 97 98 99 -187.75 -317.75 -447.75 -577.75 -707.75 -837.75 -967.75 -1097.75 2019.15 2019.15 2019.15 2019.15 2019.15 2019.15 2019.15 2019.15
100 SEG<30> 100 -1227.75 2019.15 ==============================================================================
4. PIN DESCRIPTION
SYMBOL XIN2 XOUT2 XIN1 XOUT1 RA0-RA3 Data_IO RB0-RB3 RC0-RC3 RD0-RD3 I/O I I I/O I O I O I/O FUNCTION Input pin for sub-oscillator. Connected to 32.768 KHz crystal only. Output pin for sub-oscillator with internal oscillation capacitor. Connected to 32.768 KHz crystal only. Input pin for main-oscillator. Connected to 3.58 MHz crystal or resistor to generate system clock. Output pin for main-oscillator. Connected to 3.58 MHz crystal or resistor to generate system clock. Input/Output port. Input/output mode specified by port mode 1 register (PM1). RA.3: Serial data Input/Output for electrical erasable EPROM type Input/Output port. Input/output mode specified by port mode 2 register (PM2). Input port only. Each pin has an independent interrupt capability. Input port only. This port can release hold mode but can not occur interrupt service routine.
-9-
Publication Release Date: December 2000 Revision A1
W742E/C811
Pin Description, continued
SYMBOL RE0-RE3 RF0-RF3 P00-P03
I/O O
FUNCTION Output port only. CMOS type with high sink current capacity for the LED application. Input/Output port. Input/output mode specified by port mode 6 register (PM6). P0.0 and P0.1 can be a serial I/O interface selected by SIR register. P0.0 indicates serial clock, P0.1indicates serial data.
I/O
P10-P13 Mode
I
Input port only. P1.2 & P1.3 indicates hardware interrupt(/INT0 & /INT1) P1.3: Mode select for electrical erasable EPROM type Output pin only, default in low state. This pin can output modulating or nonmodulating frequency, or Timer 1 clock output specified by mode register 1 (MR1). This pin can output dual-tone multifrequency signal for dialling. System reset pin with internal pull-high resistor. VPP: supply programming voltage, without internal pull-high resistor for electrical erasable EPROM type for avoiding high voltage programming damage
MFP DTMF
RES
O O I
VPP
SEG0-SEG31 COM0- COM15 SEG32-SEG39 (K00-K03, K10-K13) CP, CN VLCD1 VDD VSS
O O
LCD segment output pins. LCD common signal output pins. The LCD alternating frequency can be selected by code option. LCD segment output pins or DC N-MOS open drain output pins selected by code option. Connection terminals for LCD voltage double capacitor (0.1 F), tuning the capacitor value can reduce the LCD driving current. LCD supply voltage input or connect capacitor (0.1 F) to ground when enable internal pump LCD voltage Positive power supply (+). Negative power supply (-).
O I I I I
- 10 -
W742E/C811
5. FUNCTIONAL DESCRIPTION
5.1 Program Counter (PC)
Organized as an 14-bit binary counter (PC0 to PC13), the program counter generates the addresses of the 16384(16K) x 16 on-chip ROM containing the program instruction words. When the interrupt or initial reset conditions are to be executed, the corresponding address will be loaded into the program counter directly. From address 0000h to 0023h are reserved for reset and interrupt service routine. The format used is shown below. Table 1 Vector address and interrupt priority ITEM Initial Reset INT 0 (Divider0) INT 1 (Timer 0) INT 2 (Port RC) INT 3 (Port 1.2(/INT0)) INT 4 (Divider1) INT 5 (Serial I/O) INT 6 (Port1.3(/INT1)) INT 7 (Timer 1) Code Start ADDRESS 0000H 0004H 0008H 000CH 0010H 0014H 0018H 001CH 0020H 0024H INTERRUPT PRIORITY 1st 2nd 3rd 4th 5th 6th 7th 8th -
5.2 Stack Register (STACK)
The stack register is organized as 51 bits x 16 levels (first-in, last-out). When either a call subroutine or an interrupt is executed, the program counter (PC), TAB0, TAB1, TAB2, TAB3, DBKRL, DBKRH, WRP, ROMPR, PAGE, ACC and CF will be pushed into the stack register automatically. At the end of a call subroutine or an interrupt service subroutine, the RTN (only restore the program counter) and RTN #I instruction could pop the contents of the stack register into the corresponding registers. It can restore part of contents of stack buffer. When the stack register is pushed over the 16th level, the contents of the first level will be overwritten. In the other words, the stack register is always 16 levels deep. The bit definition of #I is listed below. I = 0000 0000 bit0 = 1 bit1 = 1 bit2 = 1 bit3 = 1 bit4 = 1 bit5 = 1 bit6 = 1 Pop PC from stack only Pop TAB0, TAB1, TAB2, TAB3 from stack Pop DBKRL, DBKRH from stack Pop WRP from stack Pop ROMPR from stack Pop PAGE from stack Pop ACC from stack Pop CF from stack
- 11 -
Publication Release Date: December 2000 Revision A1
W742E/C811
5.3 Program Memory (ROM)
The read-only memory (ROM) is used to store program codes or the look-up table code that can arranged up to 65536 (64K) x 4 bits. The program ROM is divided into eight pages; the size of each page is 2048(2K) x 16 bits. So the total ROM size is 16384(16K) x 16 bits. Before the jump or subroutine call instructions are to be executed, the destination ROM page register (ROMPR) must be determined firstly. The ROM page can be selected by executing the MOV ROMPR,#I or MOV ROMPR,RAM instructions. But the branch decision instructions (e.g. JB0, SKB0, JZ, JC, ...) must jump into the same ROM page. Each look-up table element is composed of 4 bits, so the look-up table can be addressed up to 65536(64K) elements. It uses instructions MOV TAB0,R MOV TAB1,R MOV TAB2,R MOV TAB3,R to determine the look-up table element address. The look-up table address is 4 times PC counter. Instruction MOVC R is used to read the look-up table content and save data into the RAM. The organization of the program memory is shown in Figure 5-1.
16 bits 0000 H: 07FFH 0800H : 0FFFH 1000H : 17FFH 1800H : 1FFFH 2000H : 27FFH 2800H : 2FFFH 3000H : 37FFH 3800H : 3FFFH Page 0 : Page 1 : Page 2 : Page 3 : Page 4 : Page 5 : Page 6 : Page 7 : 16384 * 16 bits All Program memory can be used to store instruction code or look-up table Each element (4 bits) of the look-up table
Figure 5-1 Program Memory Organization
- 12 -
W742E/C811
5.3.1 ROM Page Register (ROMPR) The ROM page register is organized as a 4-bit binary register. The bit descriptions are as follows: 3 ROMPR
Note: W means write only.
2 W
1 W
0 W
Bit 3 is reserved. Bit 2, Bit 1, Bit 0 ROM page bits: 000 = ROM page 0 (0000H - 07FFH) 001 = ROM page 1 (0800H - 0FFFH) 010 = ROM page 2 (1000H - 17FFH) 011 = ROM page 3 (1800H - 1FFFH) 100 = ROM page 4 (2000H - 27FFH) 101 = ROM page 5 (2800H - 2FFFH) 110 = ROM page 6 (3000H - 37FFH) 111 = ROM page 7 (3800H - 3FFFH) 5.3.2 ROM Addressing Mode 1. Direct Addressing Bit 13-0 PC 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
2. Far Jump or Call Bit 13-0 PC 13 P2 12 11 10 9 8 7 6 5 4 3 2 1 0
P1 P0
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
P0-2 is ROM page register(ROMPR) Example: MOV ROMPR,#I JMP or MOV ROMPR,#I Label_A
- 13 -
Publication Release Date: December 2000 Revision A1
W742E/C811
CALL 3. Conditional JMP Bit 13-0 PC 13 0 12 0 11 0 10 9 8 7 6 5 4 3 2 1 0 SUB_A
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
jmp into the same page Example: JB0 JB1 JB2 JB3 JZ JNZ JC JNC 4. Look-up Table
Bit 15-0 15 14 13 12 11 10 9 8 7 6 543 21 0 PC*4 TA33 TA32 TA31 TA30 TA23 TA22 TA21 TA20 TA13 TA12 TA11 TA10 TA03 TA02 TA01 TA00 Look-up table address = PC address*4
Lable_A0 Lable_A1 Lable_A2 Lable_A3 Label_Az Label_Anz Label_Ac Label_Anc
Example: ORG TAB_addr ; Real_TAB_addr = TAB_addr*4 TABLE 00h, 01h, 02h, 0Ah, 0Ch, 0Dh, 0Eh, 0Fh ENDT MOV MOV MOV MOV MOVC TAB0, Real_TAB_addr_B0_3 TAB1, Real_TAB_addr_B4_7 TAB2, Real_TAB_addr_B8_11 TAB3, Real_TAB_addr_B12_15 RAM ;set Look-up table address
;get Look-up table value to RAM
- 14 -
W742E/C811
5.4 Data Memory (RAM)
5.4.1 Architecture The static data memory (RAM) used to store data is arranged up to 5120(5K) x 4 bits. The data RAM is divided into 40 banks; each bank has 128 x 4 bits. Executing the MOV DBKRL,WR,MOV DBKRH,WR or MOV DBKRL,#I, MOV DBKRH,#I instructions can determine which data bank is used. The data memory can be accessed directly or indirectly and the data bank register has to be confirmed firstly. In the indirect addressing mode, each data bank will be divided into eight pages. The RAM page register has to be setting when in the indirect accessing RAM. The instructions MOV WRn,@WRq MOV @WRq,WRn could Read or Write the whole memory in the indirect addressing mode. The RAM address of @WRq indicates to (DBKRH)*800H + (DBKRL)*80H + (RAM page)*10H + (WRq). The organization of the data memory is shown in Figure 5-2.
4 bits 0000H : 007FH 0080H : 00FFH data bank 00
(or Working Registers bank) 1st data RAM page (or 1st WR page) 2nd data RAM page (or 2nd WR page) 3rd data RAM page (or 3rd WR page) : : 8th data RAM page (or 8th WR page) 70H : 7FH 00H : 0FH 10H : 1FH 20H : 2FH
data bank 01
(or Working Registers bank)
5120 address
: : : 1380H : 13FFH data bank 39 5120 * 4 bits
Figure 5-2 Data Memory Organization
The 1st and 2nd data bank (00H to 7FH & 80H to 0FFH) in the data memory can also be used as the working registers (WR). It is also divided into sixteen pages. Each page contains 16 working registers. When one page is used as Working Register, the others can be used as the normal data memory. The WR page register can be switched by executing the MOV WRP,R or MOV WRP,#I instructions. The data memory can not do the logical operation directly with the immediate data, it has to via the Working Register. 5.4.2 RAM Page Register (PAGE) The page register is organized as a 4-bit binary register. The bit descriptions are as follows: 3 PAGE
Note: R/W means read/write available.
2 R/W
1 R/W
0 R/W
Bit 3 is reserved.
- 15 -
Publication Release Date: December 2000 Revision A1
W742E/C811
Bit 2, Bit 1, Bit 0 RAM page bits: 000 = Page 0 (00H - 0FH) 001 = Page 1 (10H - 1FH) 010 = Page 2 (20H - 2FH) 011 = Page 3 (30H - 3FH) 100 = Page 4 (40H - 4FH) 101 = Page 5 (50H - 5FH) 110 = Page 6 (60H - 6FH) 111 = Page 7 (70H - 7FH) 5.4.3 WR Page Register (WRP) The WR page register is organized as a 4-bit binary register. The bit descriptions are as follows: 3 WRP R/W 2 R/W 1 R/W 0 R/W
Note: R/W means read/write available.
Bit 3, Bit 2, Bit 1, Bit 0 Working registers page bits: 0000 = WR Page 0 (00H - 0FH) 0001 = WR Page 1 (10H - 1FH) 0010 = WR Page 2 (20H - 2FH) 0011 = WR Page 3 (30H - 3FH) 0100 = WR Page 4 (40H - 4FH) 0101 = WR Page 5 (50H - 5FH) 0110 = WR Page 6 (60H - 6FH) 0111 = WR Page 7 (70H - 7FH) 1000 = WR Page 8 (80H - 8FH) 1001 = WR Page 9 (90H - 9FH) 1010 = WR Page A (A0H - AFH) 1011 = WR Page B (B0H - BFH) 1100 = WR Page C (C0H - CFH) 1101 = WR Page D (D0H - DFH) 1110 = WR Page E (E0H - EFH) 1111 = WR Page F (F0H - FFH)
- 16 -
W742E/C811
5.4.4 Data Bank Register (DBKRH, DBKRL) The data bank register is organized as two 4-bit binary register. The bit descriptions are as follows:
3 DBKRL R/W 3 DBKRH
2 R/W 2
1 R/W 1 R/W
0 R/W 0 R/W
Note: R/W means read/write available.
Bit5, Bit 4, Bit3, Bit 2, Bit 1, Bit 0 Data memory bank bits: 000000 = Data bank 0 (000H - 07FH) 000001 = Data bank 1 (080H - 0FFH) 000010 = Data bank 2 (100H - 17FH) 000011 = Data bank 3 (180H - 1FFH) 000100 = Data bank 4 (200H - 27FH) 000101 = Data bank 5 (280H - 2FFH) 000110 = Data bank 6 (300H - 37FH) 000111 = Data bank 7 (380H - 3FFH) 001000 = Data bank 8 (400H - 47FH) 001001 = Data bank 9 (480H - 4FFH) 001010 = Data bank 10 (500H - 57FH) 001011 = Data bank 11 (580H - 5FFH) 001100 = Data bank 12 (600H - 67FH) 001101 = Data bank 13 (680H - 6FFH) 001110 = Data bank 14 (700H - 77FH) 001111 = Data bank 15 (780H - 7FFH) 010000 = Data bank 16 (800H - 87FH) 010001 = Data bank 17 (880H - 8FFH) 010010 = Data bank 18 (900H - 97FH) 010011 = Data bank 19 (980H - 9FFH) 010100 = Data bank 20 (0A00H - 0A7FH) 010101 = Data bank 21 (0A80H - 0AFFH) 010110 = Data bank 22 (0B00H - 0B7FH) 010111 = Data bank 23 (0B80H - 0BFFH) 011000 = Data bank 24 (0C00H - 0C7FH) 011001 = Data bank 25 (0C80H - 0CFFH) 011010 = Data bank 26 (0D00H - 0D7FH) 011011 = Data bank 27 (0D80H - 0DFFH) Publication Release Date: December 2000 Revision A1
- 17 -
W742E/C811
011100 = Data bank 28 (0E00H - 0E7FH) 011101 = Data bank 29 (0E80H - 0EFFH) 011110 = Data bank 30 (0F00H - 0F7FH) 011111 = Data bank 31 (0F80H - 0FFFH) 100000 = Data bank 32 (1000H - 107FH) 100001 = Data bank 33 (1080H - 10FFH) 100010 = Data bank 34 (1100H - 117FH) 100011 = Data bank 35 (1180H - 11FFH) 100100 = Data bank 36 (1200H - 127FH) 100101 = Data bank 37 (1280H - 12FFH) 100110 = Data bank 38 (1300H - 137FH) 100111 = Data bank 39 (1380H - 13FFH) 5.4.5 RAM Addressing Mode 1. Direct Addressing Bit 12-0 12 11 10 9 8 7 6 5 4 3 2 1 0
RAM addr BH1 BH0 BL3 BL2 BL1 BL0 RA6 RA5 RA4 RA3 RA2 RA1 RA0 RA0-6 is RAM address ; BL0-3 is DBKRL register ; BH0-1 is DBKRH register
Example: MOV MOV MOV DBKRL,#BL_value DBKRH,#BH_value A,RAM ; set RAM bank ; get RAM data to ACC
2. Working register Addressing Bit 7-0 7 6 5 4 3 2 1 0
RAM addr WP3 WP2 WP1 WP0 WA3 WA2 WA1 WA0 WA0-3 is Working register address ; WP0-3 is WR page register(WRP)
Example: MOV MOV MOV MOVA DBKRL,#BL_value DBKRH,#BH_value WRP,#I WRn,RAM ; set RAM bank ; set WR page register ; mov RAM data to Working register and ACC
- 18 -
W742E/C811
3. Indirect Addressing Bit 12-0 12 11 10 9 8 7 6 5 4 3 2 1 0
RAM addr BH1 BH0 BL3 BL2 BL1 BL0 DP2 DP1 DP0 (WA3 WA2 WA1 WA0) (WA0-3) is Working register contents ; DP0-3 is RAM page register(PAGE) BL0-3 is DBKRL register ; BH0-1 is DBKRH register Example: MOV MOV MOV MOV MOV DBKRL,BL_value DBKRH,BH_value PAGE,#Ip WRq,#In WRn,@WRq ; set RAM bank ; set RAM page address,(0-07H) ; set WR pointer address;(0-0FH) ; get the contents of WRq pointing addr to WRn
5.5 Accumulator (ACC)
The accumulator (ACC) is a 4-bit register used to hold results from the ALU and transfer data between the memory, I/O ports, and registers.
5.6 Arithmetic and Logic Unit (ALU)
This is a circuit which performs arithmetic and logic operations. The ALU provides the following functions: * Logic operations: ANL, XRL, ORL * Branch decisions: JB0, JB1, JB2, JB3, JNZ, JZ, JC, JNC, DSKZ, DSKNZ, SKB0, SKB1, SKB2, SKB3 * Shift operations: SHRC, RRC, SHLC, RLC * Binary additions/subtractions: ADC, SBC, ADD, SUB, ADU, DEC, INC After any of the above instructions is executed, the status of the carry flag (CF) and zero flag (ZF) is stored in the internal registers. CF can be read out by executing MOV R, CF.
5.7 Main Oscillator
The W742E/C811 provides a crystal oscillation circuit to generate the system clock through external connections. The 3.58 MHz or 400 KHz crystal must be connected to XIN1 and XOUT1, and a capacitor must be connected to XIN1 and VSS if an accurate frequency is needed.
XIN1 Crystal 3.58MHz XOUT1
Figure 5-3 System clock oscillator Configuration
- 19 -
Publication Release Date: December 2000 Revision A1
W742E/C811
5.8 Sub-oscillator
The sub-oscillator is used in dual-clock operation mode. In the sub-oscillator application, just only the 32768 Hz crystal could be connected to XIN2 and XOUT2.
5.9 Dividers
Divider 0 is organized with a 14-bit binary up-counter that is designed to generate periodic interrupt. When the main clock starts action, the Divider0 is incremented by each clock (FOSC). The main clock can come from main oscillator or sub-oscillator by setting SCR register. When an overflow occurs, the Divider0 event flag is set to 1 (EVF.0 = 1). Then, if the Divider0 interrupt enable flag has been set (IEF.0 = 1), the interrupt is executed, while if the hold release enable flag has been set (HEF.0 = 1), the hold state is terminated. And the last 4-stage of the Divider0 can be reset by executing CLR DIVR0 instruction. If the main clock is connected to the 32.768K Hz crystal, the EVF.0 will be set to 1 periodically at the period of 500 mS. Divider 1 is orginized with 13/12 bits up-counter that only has sub-oscillator clock source. If the suboscillator starts action, the Divider1 is incremented by each clock (Fs). When an overflow occurs, the Divider1 event flag is set to 1 (EVF.4 = 1). Then, if the Divider1 interrupt enable flag has been set (IEF.4 = 1), the interrupt is executed, while if the hold release enable flag has been set (HEF.4 = 1), the hold state is terminated. And the last 4-stage of the Divider1 can be reset by executing CLR DIVR1 instruction. There are two period time (125 mS & 250 mS) that can be selected by setting the SCR.3 bit. When SCR.3 = 0 (default), the 250 mS period time is selected; SCR.3 = 1, the 125 mS period time is selected.
5.10 Dual-clock Operation
In this dual-clock mode, the normal operation is performed by generating the system clock from the main-oscillator clock (Fm). As required, the slow operation can be performed by generating the system clock from the sub-oscillator clock (Fs). The exchange of the normal operation and the slow operation is performed by setting the bit 0 of the System clock Control Register (SCR). If the SCR.0 is set to 0, the clock source of the system clock generator is main-oscillator clock; if the SCR.0 is set to 1, the clock source of the system clock generator is sub-oscillator clock. In the dual-clock mode, the mainoscillator can stop oscillating when the SCR.1 is set to 1. When the main clock switch, we must care the following cases: 1. X000B X011B (FOSC = Fm FOSC = Fs): We should not exchange the FOSC from Fm into Fs and disable Fm simultaneously. We could first exchange the FOSC from Fm into Fs, then disable the main-oscillator. So it should be X000BX001BX011B. 2. X011B X000B (FOSC = Fs FOSC = Fm): We should not enable Fm and exchange the FOSC from Fs into Fm simultaneously. We could first enable the main-oscillator; the 2nd step is calling a delay subroutine to wait the main-oscillator oscillating stabely; then exchange the FOSC from Fs into Fm is the last step. So it should be X011BX001Bdelay the Fm oscillating stable timeX000B. We must remember that the X010B state is inhibitive, because it will induce the system shutdown. The organization of the dual-clock operation mode is shown in Figure 5-4.
- 20 -
W742E/C811
HOLD SCR.0 XIN1 XOUT1 SCR.1
Main Oscillator
enable/disable
Fm Fs
Fosc
System Clock Generator Divider 0
T1 T2 T3 T4
STOP
XIN2 XOUT2
Sub-oscillator Divider 1
LCD Frequency Selector INT4 HCF.4
FLCD
SCR.3(13/12 bit) SCR : System clock Control Register ( default = 00H ) Bit3 Bit2 Bit1 Bit0 0 : Fosc = Fm 1 : Fosc = Fs 0 : Fm enable 1 : Fm disable 0 : WDT input clock is Fosc/2048 1 : WDT input clock is Fosc/16384 0 : 13 bit 1 : 12 bit Daul clock operation mode : - SCR.0=0, Fosc=Fm : SCR.0=1, Fosc=Fs - Flcd=Fs, In STOP mode LCD is turned off.
Figure 5-4 Organization of the dual-clock operation mode
5.11 Watchdog Timer (WDT)
The watchdog timer (WDT) is organized as a 4-bit up counter designed to prevent the program from unknown errors. The WDT can be enabled by mask option code. If the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is FOSC/1024. The input clock of the WDT can be switched to FOSC/16384 by setting SCR.2 register. The contents of the WDT can be reset by the instruction CLR WDT. In normal operation, the application program must reset WDT before it overflows. A WDT overflow indicates that operation is not under control and the chip will be reset. The WDT overflow period is about 1 S when the system clock (FOSC) is 32 KHz and WDT clock input is FOSC/2048. The organization of the Divider0 and watchdog timer is shown in Figure 5-5. The minimum WDT time interval is 1/(FOSC/16384 x 16) - 1/(FOSC/16384).
- 21 -
Publication Release Date: December 2000 Revision A1
W742E/C811
Divider0
Fosc
Q1 Q2
HEF.0
S
... Q9
EVF.0
Q
Q10 Q11 Q12 Q13 Q14
IEF.0
Hold mode release (HCF.0) Divider interrupt
R
Option code is reset to "0" SCR.2 Disable
1. Reset 2. CLR EVF,#01H 3. CLR DIVR0
WDT
Qw1 Qw2 Qw3 Qw4
R R R R
Fosc/16384 Fosc/2048
Overflow signal
System Reset
Enable Option code is set to "1"
1. Reset 2. CLR WDT
Figure 5-5 Organization of Divider0 and watchdog timer
5.12 Timer/Counter
5.12.1 Timer 0 (TM0) Timer 0 (TM0) is a programmable 8-bit binary down-counter. The specified value can be loaded into TM0 by executing the MOV TM0L(TM0H),R instructions. When the MOV TM0L(TM0H),R instructions are executed, it will stop the TM0 down-counting (if the TM0 is down-counting) and reset the MR0.3 to 0, and the specified value can be loaded into TM0. Then we can set MR0.3 to 1, that will cause the event flag 1 (EVF.1) is reset and the TM0 starts to down count. When it decrements to FFH, Timer 0 stops operating and generates an underflow (EVF.1 = 1). Then, if the Timer 0 interrupt enable flag has been set (IEF.1 = 1), the interrupt is executed, while if the hold release enable flag 1 has been set (HEF.1 = 1), the hold state is terminated. The Timer 0 clock input can be set as FOSC/1024 or FOSC/4 by setting MR0 bit 0. The default timer value is FOSC/4. The organization of Timer 0 is shown in Figure 5-6. If the Timer 0 clock input is FOSC/4: Desired Timer 0 interval = (preset value +1) x 4 x 1/FOSC If the Timer 0 clock input is FOSC/1024: Desired Timer 0 interval = (preset value +1) x 1024 x 1/FOSC Preset value: Decimal number of Timer 0 preset value FOSC: Clock oscillation frequency
- 22 -
W742E/C811
1. Reset 2. CLR EVF,#02H 3. Reset MR0.3 to 0 4.MOV TM0L,R or MOV TM0H,R MR0.0 Fosc/1024 Fosc/4 Enable Set MR0.3 to 1 MOV TM0H,R MOV TM0L,R 1. Reset 2. CLR EVF,#02H 3.Set MR0.3 to 1 Disable 8-Bit Binary Down Counter (Timer 0) 4 4 HEF.1 S R Hold mode release (HCF.1) Q EVF.1 IEF.1 Timer 0 interrupt (INT1)
Figure 5-6 Organization of Timer 0
5.12.2 Timer 1 (TM1) Timer 1 (TM1) is also a programmable 8-bit binary down counter, as shown in Figure 5-7. Timer 1 can output an arbitrary frequency to the MFP pin. The input clock of Timer 1 can be one of three sources: FOSC/64, FOSC or FS. The source can be selected by setting bit 0 and bit 1 of mode register 1 (MR1). At initial reset, the Timer 1 clock input is FOSC. When the MOV TM1L, R or MOV TM1H,R instruction is executed, the specified data are loaded into the auto-reload buffer and the TM1 down-counting will be disabled that is MR1.3 is reset to 0 at the same time. If the bit 3 of MR1 is set (MR1.3 = 1), the content of the auto-reload buffer will be loaded into the TM1 down counter, and Timer 1 starts to down count, and the event flag 7 is reset (EVF.7=0). When the timer decrements to 0FFH, it will generate an underflow (EVF.7 = 1) and be auto-reloaded with the specified data, after which it will continue to count down. Then, if interrupt enable flag 7 has been set to 1 (IEF.7 = 1), an interrupt is executed; if hold mode release enable flag 7 is set to 1 (HEF.7 = 1), the hold state is terminated. The specified frequency of Timer 1 can be delivered to the MFP output pin by programming bit 2 of MR1. Bit 3 of MR1 can be used to make Timer 1 stop or start counting. In a case where Timer 1 clock input is FT: Desired Timer 1 interval = (preset value +1) / FT Desired frequency for MFP output pin = FT / (preset value + 1) / 2 (Hz) Preset value: Decimal number of Timer 1 preset value FOSC: Clock oscillation frequency
- 23 -
Publication Release Date: December 2000 Revision A1
W742E/C811
MOV TM1H,R 4 MR1.3
MOV TM1L,R 4 S Q EVF.7 1. Reset 2. INT7 accept 3. CLR EVF, #80H 4. Set MR1.3 to 1
Auto-reload buffer MR1.1 Fs FT Fosc/64 Fosc MR1.0 Disable Enable 8 bits 8-Bit Binary Down Counter (Timer 1) Reset
R
Underflow signal
2
circuit
Reset
MFP output pin MFP signal MR1.2
Set MR1.3 to 1 MOV TM1L,R or MOV TM1H,R
Figure 5-7 Organization of Timer 1
For example, when FT equals 32768 Hz, depending on the preset value of TM1, the MFP pin will output a single tone signal in the tone frequency range from 64 Hz to 16384 Hz. The relation between the tone frequency and the preset value of TM1 is shown in the table below. Table 2 The relation between the tone frequency and the preset value of TM1
3rd octave
Tone frequency TM1 preset value & MFP frequency 7CH 75H 6FH 68H 62H 5DH 58H 53H 4EH 49H 45H 41H 131.07 138.84 146.28 156.03 165.49 174.30 184.09 195.04 207.39 221.40 234.05 248.24
4th octave
Tone frequency 261.63 277.18 293.66 311.13 329.63 349.23 369.99 392.00 415.30 440.00 466.16 493.88 TM1 preset value & MFP frequency 3EH 3AH 37H 34H 31H 2EH 2BH 29H 26H 24H 22H 20H 260.06 277.69 292.57 309.13 327.68 372.36 390.09 420.10 443.81 442.81 468.11 496.48
5th octave
Tone frequency 523.25 554.37 587.33 622.25 659.26 698.46 739.99 783.99 830.61 880.00 932.23 987.77 TM1 preset value & MFP frequency 1EH 1CH 1BH 19H 18H 16H 15H 14H 13H 12H 11H 10H 528.51 564.96 585.14 630.15 655.36 712.34 744.72 780.19 819.20 862.84 910.22 963.76
C C# D
130.81 138.59 146.83 155.56 164.81 174.61 185.00 196.00 207.65 220.00 233.08 246.94
T O N E
D# E F F# G G# A A# B
Note: Central tone is A4 (440 Hz).
- 24 -
W742E/C811
5.13 Mode Register 0 (MR0)
Mode Register 0 is organized as a 4-bit binary register (MR0.0 to MR0.3). MR0 can be used to control the operation of Timer 0. The bit descriptions are as follows: 3 MR0
Note: W means write only.
2
1
0 W
W
Bit 0 = 0 =1 Bit 3 = 0 =1
The fundamental frequency of Timer 0 is FOSC/4. The fundamental frequency of Timer 0 is FOSC/1024. Timer 0 stops down-counting. Timer 0 starts down-counting.
Bit 1 & Bit 2 are reserved
5.13.1 Mode Register 1 (MR1) Mode Register 1 is organized as a 4-bit binary register (MR1.0 to MR1.3). MR1 can be used to control the operation of Timer 1. The bit descriptions are as follows: 3 MR1
Note: W means write only.
2 W
1 W
0 W
W
Bit 0 Bit 1
=0 =1 =0 =0 =0 =1 =0 =1
Bit 2 Bit 3
The internal fundamental frequency of Timer 1 is FOSC. The internal fundamental frequency of Timer 1 is FOSC/64. The fundamental frequency source of Timer1 is the internal clock. The fundamental frequency source of Timer1 is the sub-oscillator frequency Fs (32.768 KHz). The specified waveform of the MFP generator is delivered at the MFP output pin. The specified frequency of Timer 1 is delivered at the MFP output pin. Timer 1 stops down-counting. Timer 1 starts down-counting.
5.14 Interrupts
The W742E/C811 provides four internal interrupt sources (Divider 0, Divider 1, Timer 0, Timer 1) and seven external interrupt source (port P1.2(/INT 0), RC.0-3, Serial port, P1.3(/INT1)). Vector addresses for each of the interrupts are located in the range of program memory (ROM) addresses 004H to 023H. The flags IEF, PEF, and EVF are used to control the interrupts. When EVF is set to "1" by hardware and the corresponding bits of IEF and PEF have been set by software, an interrupt is generated. When an interrupt occurs, the corresponding bit of EVF will be clear, and all of the interrupts will be inhibited until the EN INT or MOV IEF,#I instruction is invoked. Normally, the EN INT instruction will be asserted before the RTN instruction. The interrupts can also be disabled
- 25 -
Publication Release Date: December 2000 Revision A1
W742E/C811
by executing the DIS INT instruction. When an interrupt is generated in the hold mode, the hold mode will be released momentarily and interrupt service routine will be executed. After executing interrupt service routine, the C will enter hold mode automatically. The operation flow chart is shown in Figure 5-9. The control diagram is shown Figure 5-8.
Initial Reset Enable
Divider 0 overflow signal
EN INT MOV IEF,#I S R Q EVF.0
IEF.0 EVF.1 IEF.1
Timer 0 underflow signal
S R
Q
Interrupt Process Circuit
Interrupt Vector Generator
004H 008H 020H
RC.0-3 signal S R Q
EVF.2 IEF.2
P1.2 (/INT0) signal S R Divider 1 overflow signal Q
EVF.3 IEF.3
S R
Q
EVF.4 IEF.4
Serial I/O signal
S R
Q
EVF.5 IEF.5
P1.3(/INT1) signal
S R
Q
EVF.6 IEF.6
Timer 1 underflow signal
S R
Q
EVF.7 IEF.7
Disable Initial Reset CLR EVF,#I instruction
DIS INT instruction
Figure 5-8 Interrupt event control diagram
- 26 -
W742E/C811
5.15 Stop Mode Operation
In stop mode, all operations of the C cease. The C enters stop mode when the STOP instruction is executed and exits stop mode when an external trigger is activated (by a falling signal on the RC or RD port). When the designated signal is accepted, the C awakens and executes the next instruction. In the dual-clock slow operation mode, the STOP instruction will disable both the main-oscillator and suboscillator oscillating; To avoid erroneous execution, the NOP instruction should follow the STOP command. 5.15.1 Stop Mode Wake-up Enable Flag for RC and RD Port (SEF) The stop mode wake-up flag for port RC and RD is organized as an 8-bit binary register (SEF.0 to SEF.7). Before port RC and RD can be used to exit the stop mode, the content of the SEF must be set first. The SEF is controlled by the MOV SEF, #I instruction. The bit descriptions are as follows: 7 SEF w 6 w 5 w 4 w 3 w 2 w 1 w 0 w
Note: W means write only.
SEF.0 = 1 Device will exit stop mode when a falling edge signal is applied to pin RC.0 SEF.1 = 1 Device will exit stop mode when a falling edge signal is applied to pin RC.1 SEF.2 = 1 Device will exit stop mode when a falling edge signal is applied to pin RC.2 SEF.3 = 1 Device will exit stop mode when a falling edge signal is applied to pin RC.3 SEF.4 = 1 Device will exit stop mode when a falling edge signal is applied to pin RD.0 SEF.5 = 1 Device will exit stop mode when a falling edge signal is applied to pin RD.1 SEF.6 = 1 Device will exit stop mode when a falling edge signal is applied to pin RD.2 SEF.7 = 1 Device will exit stop mode when a falling edge signal is applied to pin RD.3
5.16 Hold Mode Operation
In hold mode, all operations of the C cease, except for the operation of the oscillator, Timer, Divider, and LCD driver. The C enters hold mode when the HOLD instruction is executed. The hold mode can be released in one of nine ways: by the action of timer 0, timer 1, divider 0, divider 1, RC port, P1.2 ( INT0 ), Serial I/O, P1.3 ( INT1 ) and RD port. Before the device enters the hold mode, the HEF, HEFD, PEF, and IEF flags must be set to control the hold mode release conditions. When any of the HCF bits is "1," the hold mode will be released. Regarding to RC and RD port, PSR0 and PSR1 registers indicate signal change on which pin of the port. The HCF and HCFD are set by hardware and clear by software. When EVF, EVFD and HEF, HEFD have been reset by the CLR EVF,#I CLR EVFD and MOV HEF,#I CLR HEFD instructions, the corresponding bit of HCF, HCFD is reset simultaneously. The HCF and HCFD should be clear every time before enter the hold mode. For more details, refer to the following flow chart.
- 27 -
Publication Release Date: December 2000 Revision A1
W742E/C811
Divider 0, Divider 1, Timer 0, Timer 1, Signal Change at RC,RD port, falling edge at P1.2,P1.3, Serial I/O
Yes
In HOLD Mode?
No
Interrupt Enable? Yes
No
Interrupt Enable? Yes
No
IEF Flag Set? Yes Reset EVF Flag Execute Interrupt Service Routine (Note)
No
IEF Flag Set? Yes Reset EVF Flag Execute Interrupt Service Routine Yes (Hold release)
No
HEF Flag Set? No
(Note)
Disable interrupt
Disable interrupt
HOLD
PC <- (PC+1)
Note: The bit of EVF corresponding to the interrupt signal will be reset. ** The RD port can not occur interrupt service , it only can release hold mode.
Figure 5-9 Hold Mode and Interrupt Operation Flow Chart
- 28 -
W742E/C811
5.16.1 Hold Mode Release Enable Flag (HEF, HEFD) The hold mode release enable flag is organized on an 8-bit binary register (HEF.0 to HEF.7) and a 1bit register (HEFD). The HEF and HEFD are used to control the hold mode release conditions. It is controlled by the MOV HEF, #I, MOV HEFD,#I instructions. The bit descriptions are as follows: 7 HEF w 6 w 5 w 4 w 3 w 2 w 1 w 0 w 0 HEFD
Note: W means write only.
w
HEF.0 = 1 Overflow from the Divider 0 causes Hold mode to be released. HEF.1 = 1 Underflow from Timer 0 causes Hold mode to be released. HEF.2 = 1 Signal change at port RC causes Hold mode to be released. HEF.3 = 1 Falling edge signal at port P1.2 (/INT0) causes Hold mode to be released. HEF.4 = 1 Overflow from the Divider 1 causes Hold mode to be released. HEF.5 = 1 Serial I/O HEF.6 = 1 Falling edge signal at port P1.3 (/INT1) causes Hold mode to be released. HEF.7 = 1 Underflow from Timer 1 causes Hold mode to be released. HEFD = 1 Signal change at port RD causes Hold mode to be released.
5.16.2 Interrupt Enable Flag (IEF) The interrupt enable flag is organized as a 8-bit binary register (IEF.0 to IEF.7). These bits are used to control the interrupt conditions. It is controlled by the MOV IEF, #I instruction. When one of these interrupts is occurred, the corresponding event flag will be clear, but the other bits are unaffected. In interrupt subroutine, these interrupts will be disable till the instruction MOV IEF, #I or EN INT is executed again. However, these interrupts can be disable by executing DIS INT instruction. The bit descriptions are as follows: 7 IEF w 6 w 5 w 4 w 3 w 2 w 1 w 0 w
Note: W means write only.
IEF.0 = 1 Interrupt 0 is accepted by overflow from the Divider 0. IEF.1 = 1 Interrupt 1 is accepted by underflow from the Timer 0. IEF.2 = 1 Interrupt 2 is accepted by a signal change at port RC. IEF.3 = 1 Interrupt 3 is accepted by a falling edge signal at port P1.2 (/INT0). IEF.4 = 1 Interrupt 4 is accepted by overflow from the Divider 1.
- 29 -
Publication Release Date: December 2000 Revision A1
W742E/C811
IEF.5 = 1 Interrupt 5 is accepted by Serial I/O signal IEF.6 = 1 Interrupt 6 is accepted by a falling edge signal at port P1.3 (/INT1). IEF.7 = 1 Interrupt 7 is accepted by underflow from Timer 1.
5.16.3 Port Enable Flag (PEF, P1EF) The port enable flag is organized as 8-bit binary register (PEF.0 to PEF.7) and 4-bit register (P1EF.2 and P1EF.3). Before port RC, RD may be used to release the hold mode, the content of the PEF must be set first. The PEFand P1EF are controlled by the MOV PEF, #I MOV P1EF,#I instructions. The bit descriptions are as follows. Besides release hold mode, the RC port can be bit controlled individually to perform interrupt function. 7 PEF w 3 P1EF
Note: W means write only.
6 w 2 w
5 w 1 -
4 w 0 -
3 w
2 w
1 w
0 w
w
PEF.0: Enable/disable the signal change at pin RC.0 to release hold mode or perform interrupt. PEF.1: Enable/disable the signal change at pin RC.1 to release hold mode or perform interrupt. PEF.2: Enable/disable the signal change at pin RC.2 to release hold mode or perform interrupt. PEF.3: Enable/disable the signal change at pin RC.3 to release hold mode or perform interrupt. PEF.4: Enable/disable the signal change at pin RD.0 to release hold mode. PEF.5: Enable/disable the signal change at pin RD.1 to release hold mode. PEF.6: Enable/disable the signal change at pin RD.2 to release hold mode. PEF.7: Enable/disable the signal change at pin RD.3 to release hold mode. P1EF.2: Enable/disable the falling edge signal at P1.2 to release hold mode. P1EF.3: Enable/disable the falling edge signal at P1.3 to release hold mode.
5.16.4 Hold Mode Release Condition Flag (HCF, HCFD) The hold mode release condition flag is organized as 8-bit binary register (HCF.0 to HCF.7) and HCFD. It indicates which one releases the hold mode, and is set by hardware. The HCF can be read out by the MOVA R, HCFL and MOVA R, HCFH instructions. When any of the HCF bits is "1," the hold mode will be released. But the HCFD can not be read, it is only for internal flag. It records the port RD releasing the hold mode. The HCF and HCFD are set by hardware and clear by software. The HCF and HCFD should be clear every time before enter the hold mode. When EVF, EVFD and HEF, HEFD have been reset, the corresponding bit of HCF, HCFD is reset simultaneously. The bit descriptions are as follows:
- 30 -
W742E/C811
7 HCF R 6 R 5 R 4 R 3 R 2 R 1 R 0 R
HCFD: internal flag, can not be read
Note: R means read only.
HCF.0 = 1 Hold mode was released by overflow from the divider 0. HCF.1 = 1 Hold mode was released by underflow from the timer 0. HCF.2 = 1 Hold mode was released by a signal change at port RC. HCF.3 = 1 Hold mode was released by a signal change at port P1.2 (/INT0). HCF.4 = 1 Hold mode was released by overflow from the divider 1. HCF.5 = 1 Hold mode was released by Serial I/O signal. HCF.6 = 1 Hold mode was released by a signal change at port P1.3 (/INT1). HCF.7 = 1 Hold mode was released by underflow from the timer 1. HCFD = 1 Hold mode was released by a signal change at port RD.
5.16.5 Event Flag (EVF,EVFD) The event flag is organized as a 8-bit binary register (EVF.0 to EVF.7) and EVFD. It is set by hardware and reset by CLR EVF,#I ,CLR EVFD instructions or the interrupt occurrence. The bit descriptions are as follows: 7 EVF EVFD
Note: R/W means read/write.
6
5 R/W
4 R/W
3 R/W
2 R/W
1 R/W
0 R/W
R/W R/W R/W
EVF.0 = 1 Overflow from divider 0 occurred. EVF.1 = 1 Underflow from timer 0 occurred. EVF.2 = 1 Signal change at port RC occurred. EVF.3 = 1 Falling edge signal at port P1.2 ( INT0 ) occurred. EVF.4 = 1 Overflow from divider 1 occurred. EVF.5 = 1 Serial I/O occurred. EVF.6 = 1 Falling edge signal at port P1.3 ( INT1 ) occurred. EVF.7 = 1 Underflow from Timer 1 occurred. EVFD = 1 Signal change at port RD occurred.
- 31 -
Publication Release Date: December 2000 Revision A1
W742E/C811
5.17 Reset Function
The W742E/C811 is reset either by a power-on reset or by using the external RES pin. The initial state of the W742E/C811 after the reset function is executed is described below.
Table 3 The initial state after the reset function is executed Program Counter (PC) TM0, TM1 MR0, MR1, PAGE registers PSR0, PSR1, PSR2, SCR registers IEF, HEF,HEFD, HCF, PEF, P1EF, EVF, EVFD, SEF flags WRP, DBKR register Timer 0 input clock Timer 1 input clock MFP output DTMF output Input/output ports RA,RB, P0 Output port RE & RF RA, RB & P0 ports output type RC,RD ports pull-high resistors Input clock of the watchdog timer LCD display 000H Reset Reset Reset Reset Reset FOSC/4 FOSC Low Hi-Z Input mode High CMOS type Disable FOSC/1024 OFF
5.18 Input/Output Ports RA, RB & P0
Port RA consists of pins RA.0 to RA.3. Port RB consists of pins RB.0 to RB.3. Port P0 consists of pins P0.0 to P0.3. At initial reset, input/output ports RA, RB and P0 are all in input mode. When RA and RB are used as output ports, CMOS or NMOS open drain output type can be selected by the PM0 register. But when P0 is used as output port, the output type is just fixed to be CMOS output type. Each pin of port RA, RB and P0 can be specified as input or output mode independently by the PM1, PM2 and PM6 registers. The MOVA R, RA or MOVA R, RB or MOVA R, P0 instructions operate the input functions and the MOV RA, R or MOV RB, R or MOV P0, R operate the output functions. For more detail port structure, refer to the and Figure 5-10 and Figure 5-10.
- 32 -
W742E/C811
Input/Output Pin of the RA(RB)
PM0.0(PM0.1)
DATA BUS
Output Buffer
Enable
I/O PIN RA.n(RB.n)
PM1.n (PM2.n)
MOV RA,R(MOV RB,R) instruction
Enable
MOVA R,RA(MOVA R,RB) instruction
Figure 5-10 Architecture of RA (RB) Input/Output Pins
Input/Output Pin of the P0
DATA BUS
Output Buffer
Enable
I/O PIN P0.n
PM6.n
MOV P0,R instruction
Enable
MOVA R,P0 instruction
Figure 5-11 Architecture of P0 Input/Output pins
5.18.1 Port Mode 0 Register (PM0) The port mode 0 register is organized as 4-bit binary register (PM0.0 to PM0.3). PM0 can be used to determine the port structure; it is controlled by the MOV PM0, #I instruction. The bit description is as follows: 3 PM0
Note: W means write only.
2 w
1 w
0 w
w
Bit 0 = 0 RA port is CMOS output type. Bit 1 = 0 RB port is CMOS output type.
Bit 0 = 1 RA port is NMOS open drain output type. Bit 1 = 1 RB port is NMOS open drain output type.
Bit 2 = 0 RC port pull-high resistor is disabled. Bit 2 = 1 RC port pull-high resistor is enabled. Bit 3 = 0 RD port pull-high resistor is disabled. Bit 3 = 1 RD port pull-high resistor is enabled.
- 33 -
Publication Release Date: December 2000 Revision A1
W742E/C811
5.18.2 Port Mode 1 Register (PM1) The port mode 1 register is organized as 4-bit binary register (PM1.0 to PM1.3). PM1 can be used to control the input/output mode of port RA. PM1 is controlled by the MOV PM1, #I instruction. The bit description is as follows: 3 PM1
Note: W means write only.
2 w
1 w
0 w
w
Bit 0 = 0 RA.0 works as output pin; Bit 0 = 1 RA.0 works as input pin Bit 1 = 0 RA.1 works as output pin; Bit 1 = 1 RA.1 works as input pin Bit 2 = 0 RA.2 works as output pin; Bit 2 = 1 RA.2 works as input pin Bit 3 = 0 RA.3 works as output pin; Bit 3 = 1 RA.3 works as input pin At initial reset, port RA is input mode (PM1 = 1111B).
5.18.3 Port Mode 2 Register (PM2) The port mode 2 register is organized as 4-bit binary register (PM2.0 to PM2.3). PM2 can be used to control the input/output mode of port RB. PM2 is controlled by the MOV PM2, #I instruction. The bit description is as follows: 3 PM2 w 2 w 1 w 0 w
Note: W means write only.
Bit 0 = 0 RB.0 works as output pin; Bit 0 = 1 RB.0 works as input pin Bit 1 = 0 RB.1 works as output pin; Bit 1 = 1 RB.1 works as input pin Bit 2 = 0 RB.2 works as output pin; Bit 2 = 1 RB.2 works as input pin Bit 3 = 0 RB.3 works as output pin; Bit 3 = 1 RB.3 works as input pin At initial reset, the port RB is input mode (PM2 = 1111B). 5.18.4 Port Mode 6 Register (PM6) The port mode 6 register is organized as 4-bit binary register (PM6.0 to PM6.3). PM6 can be used to control the input/output mode of port P0. PM6 is controlled by the MOV PM6, #I instruction. The bit description is as follows: 3 PM6 w 2 w 1 w 0 w
Note: W means write only.
- 34 -
W742E/C811
Bit 0 = 0 P0.0 works as output pin; Bit 0 = 1 P0.0 works as input pin Bit 1 = 0 P0.1 works as output pin; Bit 1 = 1 P0.1 works as input pin Bit 2 = 0 P0.2 works as output pin; Bit 2 = 1 P0.2 works as input pin Bit 3 = 0 P0.3 works as output pin; Bit 3 = 1 P0.3 works as input pin At initial reset, the port P0 is input mode (PM6 = 1111B).
5.18.5 Serial I/O Interface The bit 0 and bit 1 of port P0 can be used as a serial input/output port. P0.0 is the serial clock I/O pin and P0.1 is the serial data I/O pin. A 4-bit binary register, Serial Interface Control register (SIC), controls the serial port. SIC is controlled by the MOV SIC,#I instruction. The bit definition is as follow: 3 SIC w 2 w 1 w 0 w
Bit 0 = 0 P0.0 & P0.1 work as normal input/output pin; Bit 0 = 1 P0.0 & P0.1 work as serial port function. Bit 1 = 0 P0.0 works as serial clock input pin; Bit 1 = 1 P0.0 works as serial clock output pin. Bit 2 = 0 Serial data latched/changed at falling edge of clock; Bit 2 = 1 Serial data latched/changed at rising edge of clock. Bit 3 = 0 Serial clock output frequency is fosc/2; Bit 3 = 1 Serial clock output frequency is fosc/256. At initial reset, SIC = 0000B. The serial I/O functions are controlled by the instructions SOP R and SIP R. The two instructions are described below: (1) When in the first time the SIP R instruction is executed, the data will be loaded to the ACC and RAM from the serial input buffer. But this data is not meaningful, it is used to enable serial port. There are two methods to get the serial data, one is interrupt and the other is polling. When enable the serial input, the bit 1 of port status register 2(PRS2) will automatically be set to "1" (BUSYI = 1). Then the P0.0 pin will send out 8 clocks or accept 8 clcoks from external device and the data from the P0.1 pin will be loaded to SIB buffer at the rising or falling edge of the P0.0 pin. After the 8 clocks have been sent, BUSYI will be reset to "0" and EVF.5 will be set to "1." At this time, if IEF.5 has been set (IEF.5 = 1), an interrupt is executed then the SIP R instruction can get the correct data from the serial input buffer (SIB), low nibble of SIB movs to ACC register and the high nibble moves to RAM; if HEF.5 has been set (HEF.5 = 1), the hold state is terminated. The polling method is to check the status of PSR2.1 (BUSYI) to know whether the serial input process is completed or not. If a serial input process is not completed, but the SIP R instruction is executed again, the data will be lost. The timing is shown in Figure 5-12.
- 35 -
Publication Release Date: December 2000 Revision A1
W742E/C811
T1 T2 T3 T4 Ins.
rising latch
SIP R 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8
P0.0 P0.0
falling latch
Data latch BUSYI
(PSR2.1)
EVF5 P0.1
NOTE: The serial clock frequency is fosc/2
Figure 5-12 Timing of the Serial Input Function (SIP R)
(2) When the SOP R instruction is executed, the data will be loaded to the serial output buffer (SOB) from ACC and the RAM, the low nibble data of SOB is from ACC register and the high nibble data is from RAM, and bit 3 of port status register 2(PSR2) will be set to "1" (BUSYO = 1). Then the P0.0 pin will send out 8 clocks or accept 8 clocks from external device and the data in SOB will be sent out at the rising or falling edge of the P0.1 pin. After the 8 clocks have been sent, BUSYO will be reset to "0" and EVF.5 will be set to "1." At this time, if IEF.5 has been set (IEF.5 = 1), an interrupt is executed; if HEF.5 has been set (HEF.5 = 1), the hold state is terminated. Users can check the status of PSR2.3 (BUSYO) to know whether the serial output process is completed or not. If a serial output process is not completed, but the SOP R instruction is executed again, the data will be lost. The timing is shown in Figure 5-13.
- 36 -
W742E/C811
T1 T2 T3 T4 Ins.
data changed at falling edge
SOP R 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8
P0.0
data changed at rising edge
P0.0
Data latch BUSYO
(PSR2.3)
EVF5 P0.1
NOTE: The serial clock frequency is fosc/2
Figure 5-13 Timing of the Serial Output Function (SOP R)
Port Status Register 2 (PSR2)
Port status register 2 is organized as 4-bit binary register (PSR2.0 to PSR2.3). PSR2 is controlled by the MOVA R, PSR2, and CLR PSR2 instructions. The bit descriptions are as follows: 3 PSR2 R 2 1 R 0
Note: R means read only.
Bit 0 is reserved. Bit 1 (BUSYI): Serial port input busy flag. Bit 2 is reserved. Bit 3 (BUSYO): Serial port output busy flag.
5.19 Input Ports RC
Port RC consists of pins RC.0 to RC.3. Each pin of port RC can be connected to a pull-high resistor, which is controlled by the port mode 0 register (PM0). When the PEF, HEF, and IEF corresponding to the RC port are set, a signal change at the specified pins of port RC will execute the hold mode
- 37 -
Publication Release Date: December 2000 Revision A1
W742E/C811
release or interrupt subroutine. Port status register 0 (PSR0) records the status of signal changes on the pins of port RC. PSR0 can be read out and cleared by the MOVA R, PSR0, and CLR PSR0 instructions. In addition, the falling edge signal on the pin of port RC specified by the instruction MOV SEF, #I will cause the device to exit the stop mode. Refer to Figure 5-14 and the instruction table for more details.
DATA BUS PM0.2 Signal change detector PEF.0 D Q ck R PSR0.0
RC.0
HEF.2 PM0.2 Signal change detector PEF.1 D Q ck R PSR0.1 D ck R IEF.2 Q EVF.2
HCF.2
RC.1
INT 2
PM0.2 Signal change detector PEF.2 D Q ck R PSR0.2
RC.2
CLR EVF, #I Reset
PM0.2 Signal change detector
PEF.3 D Q ck R PSR0.3
RC.3
SEF.0 Falling Edge detector SEF.1 Falling Edge detector SEF.2 Falling Edge detector SEF.3 Falling Edge detector
Reset MOV PEF, #I CLR PSR0
To Wake Up Stop Mode
Figure 5-14 Architecture of Input Ports RC
- 38 -
W742E/C811
5.19.1 Port Status Register 0 (PSR0) Port status register 0 is organized as 4-bit binary register (PSR0.0 to PSR0.3). PSR0 can be read or cleared by the MOVA R, PSR0, and CLR PSR0 instructions. The bit descriptions are as follows: 3 PSR0 R 2 R 1 R 0 R
Note: R means read only.
Bit 0 = 1 Bit 1 = 1 Bit 2 = 1 Bit 3 = 1
Signal change at RC.0 Signal change at RC.1 Signal change at RC.2 Signal change at RC.3
5.20 Input Ports RD
Port RD consists of pins RD.0 to RD.3. Each pin of port RD can be connected to a pull-high resistor, which is controlled by the port mode 0 register (PM0). When the PEF and HEFD corresponding to the RD port are set, a signal change at the specified pins of port RD will execute the hold mode release. Port status register 1 (PSR1) records the status of signal changes on the pins of port RD. PSR1 can be read out and cleared by the MOVA R, PSR1, and CLR PSR1 instructions. In addition, the falling edge signal on the pin of port RD specified by the instruction MOV SEF, #I will cause the device to exit the stop mode. Refer to Figure 5-15 and the instruction table for more details.
- 39 -
Publication Release Date: December 2000 Revision A1
W742E/C811
DATA BUS PM0.3 Signal change detector PEF.4 D Q ck R PSR1.0
RD.0
HEFD PM0.3 Signal change detector PEF.5 D Q ck R PSR1.1 D ck R Q EVFD
HCFD
RD.1
PM0.3 Signal change detector
PEF.6 D Q ck R PSR1.2
RD.2
CLR EVFD Reset
PM0.3 Signal change detector
PEF.7 D Q ck R PSR1.3
RD.3
SEF.4 Falling Edge detector SEF.5 Falling Edge detector SEF.6 Falling Edge detector SEF.7 Falling Edge detector
Reset MOV PEF, #I CLR PSR1
To Wake Up Stop Mode
Figure 5-15 Architecture of Input Ports RD
5.20.1 Port Status Register 1 (PSR1) Port status register 1 is organized as 4-bit binary register (PSR1.0 to PSR1.3). PSR1 can be read or cleared by the MOVA R, PSR1, and CLR PSR1 instructions. The bit descriptions are as follows: 3 PSR1
Note: R means read only.
2 R
1 R
0 R
R
- 40 -
W742E/C811
Bit 0 = 1 Bit 1 = 1 Bit 2 = 1 Bit 3 = 1 Signal change at RD.0 Signal change at RD.1 Signal change at RD.2 Signal change at RD.3
5.21 Output Port RE & RF
Output port RE and RF are used as output of the internal RT port. When the MOV RE, R or MOV RF, R instruction is executed, the data in the RAM will be output to port RT through port RE or RF. They provide high sink current to drive LED.
5.22 Input Port P1
Input port P1 is a multi-function input port. When the MOVA R, P1 instruction is executed, the P1 data will be get to the RAM and A register. The P1.2 and P1.3 can be configurated as the external interrupt /INT0 and /INT1 by set P1EF.2 and P1EF.3.
5.23 DTMF Output Pin (DTMF)
W742E/C811 provides a DTMF generator which outputs the dual tone multi-frequency signal to the DTMF pin. The DTMF generator can work well at the operating frequency of 3.58 MHz. A DTMF register specify the desired low/high frequency. And the Dual Tone Control Register (DTCR) can control whether the dual tone will be output or not. The tones are divided into two groups (low group and high group). The relation between the DTMF signal and the corresponding touch tone keypad is shown in Figure 5-16.
C1 R1 1
C2
C3
C4 Row/Col Frequency 697 Hz 770 Hz 852 Hz 941 Hz 1209 Hz 1336 Hz 1477 Hz 1633 Hz
2
3
A
R1 R2 R3 R4 C1 C2 C3 C4
R2
4
5
6
B
R3
7
8
9
C
R4
*
0
#
D
Figure 5-16 The relation between the touch tone keypad and the frequency
- 41 -
Publication Release Date: December 2000 Revision A1
W742E/C811
5.23.1 DTMF register DTMF register is organized as 4-bit binary register. By controlling the DTMF register, one tone of the low/high group can be selected. The MOV DTMF, R instruction can specify the wanted tones. The bit descriptions are as follows: 3 DTMF
Note: W means write only.
2 W
1 W
0 W
W
b3 X High Group X X X 0 Low Group 0 1 1
Note: X means this bit do not care.
b2 X X X X 0 1 0 1
b1 0 0 1 1 X X X X
b0 0 1 0 1 X X X X
Selected Tone 1209 Hz 1336 Hz 1477 Hz 1633 Hz 697 Hz 770 Hz 852 Hz 941 Hz
5.23.2 Dual Tone Control Register (DTCR) Dual tone control register is organized as 4-bit binary register. The output of the dual or single tone will be controlled by this register. The MOV DTCR,#I instruction can specify the wanted status. The bit descriptions are as follows: 3 DTCR
Note: W means write only.
2 W
1 W
0 W
Bit 0 = 1 Bit 1 = 1 Bit 2 = 1
Low group tone output is enabled. High group tone output is enabled. DTMF output is enabled. When Bit 2 is reset to 0, the DTMF output pin will be Hi-Z state.
Bit 3 is reserved.
5.24 MFP Output Pin (MFP)
The MFP output pin can select the output of the Timer 1 clock or the modulation frequency; the output of the pin is determined by mode register 1 (MR1). The organization of MR1 is shown in Figure 5-7. When bit 2 of MR1 is reset to "0," the MFP output can deliver a modulation output in any combination - 42 -
W742E/C811
of one signal from among DC, 4096 Hz, 2048 Hz, and one or more signals from among 128 Hz, 64 Hz, 8 Hz, 4 Hz, 2 Hz, or 1 Hz (the clock source is from 32.768 KHz crystal). The MOV MFP, #I instruction is used to specify the modulation output combination. The data specified by the 8-bit operand and the MFP output pin are shown in next page. Table 4 The relation between the MFP output frequncy and the data specified by 8-bit operand
(Fosc = 32.768 KHz)
R7 R6
R5 0 0 0
R4 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0
R3 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0
R2 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0
R1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0
R0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 128 Hz 64 Hz 8 Hz 4 Hz 2 Hz 1 Hz
FUNCTION Low level
00
0 0 0 1 0 0 0
High level 128 Hz 64 Hz 8 Hz 4 Hz 2 Hz 1 Hz 2048 Hz 2048 Hz * 128 Hz 2048 Hz * 64 Hz 2048 Hz * 8 Hz 2048 Hz * 4 Hz 2048 Hz * 2 Hz 2048 Hz * 1 Hz 4096 Hz 4096 Hz * 128 Hz 4096 Hz * 64 Hz 4096 Hz * 8 Hz 4096 Hz * 4 Hz 4096 Hz * 2 Hz 4096 Hz * 1 Hz
01
0 0 0 1 0 0 0
10
0 0 0 1 0 0 0
11
0 0 0 1
- 43 -
Publication Release Date: December 2000 Revision A1
W742E/C811
5.25 LCD Controller/Driver
The W742E/C811 can directly drive an LCD with 40 segment output pins and 16 common output pins for a total of 40 x 16 dots. The LCD driving mode is 1/5 bias 1/8 or 1/16 duty. The alternating frequency of the LCD can be set as Fw/16, Fw/32, Fw/64, or Fw/128. The structure of the LCD alternating frequency (FLCD) is shown in the Figure 5-17.
Sub-oscillator clock
Fw
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Fw/16 Fw/32 Fw/64 Fw/128
Selector
FLCD
Figure 5-17 LCD alternating frequency (FLCD) circuit diagram
Fw = 32.768 KHz, the LCD frequency is as shown in the table below. Table 5 The relartionship between the FLCD and the duty cycle LCD Frequency Fw/128 (256 Hz) Fw/64 (512 Hz) Fw/32 (1024 Hz) Fw/16 (2048 Hz) 1/8 duty 32 64 128 1/16 duty 32 64 128
- 44 -
W742E/C811
Corresponding to the 40 LCD drive output pins, there are 160 LCD data RAM segments. Instructions such as MOV LPL,R, MOV LPH,R, MOV @LP,R, and MOV R,@LP are used to control the LCD data RAM. The data in the LCD data RAM are transferred to the segment output pins automatically without program control. When the bit value of the LCD data RAM is "1," the LCD is turned on. When the bit value of the LCD data RAM is "0," LCD is turned off. The contents of the LCD data RAM (LCDR) are sent out through the segment0 to segment39 pins by a direct memory access. The relation between the LCD data RAM and segment/common pins is shown below. Table 6 The reation between the LCDR and segment/common pins used as LCD drive output pins
OUTPUT PIN SEG0 SEG1 : : SEG38 SEG39 OUTPUT PIN SEG0 SEG1 : : SEG38 SEG39 LCD RAM LCDR01 LCDR03 : : LCDR4D LCDR4F LCD RAM LCDR81 LCDR83 : : LCDRCD LCDRCF COM7 BIT3 0/1 0/1 : : 0/1 0/1 COM15 BIT3 0/1 0/1 : : 0/1 0/1 COM6 BIT2 0/1 0/1 : : 0/1 0/1 COM14 BIT2 0/1 0/1 : : 0/1 0/1 COM5 BIT1 0/1 0/1 : : 0/1 0/1 COM13 BIT1 0/1 0/1 : : 0/1 0/1 COM4 BIT0 0/1 0/1 : : 0/1 0/1 COM12 BIT0 0/1 0/1 : : 0/1 0/1 LCD RAM LCDR00 LCDR02 : : LCDR4C LCDR4E LCD RAM LCDR80 LCDR82 : : LCDRCC LCDRCE COM3 BIT3 0/1 0/1 : : 0/1 0/1 COM11 BIT3 0/1 0/1 : : 0/1 0/1 COM2 BIT2 0/1 0/1 : : 0/1 0/1 COM10 BIT2 0/1 0/1 : : 0/1 0/1 COM1 BIT1 0/1 0/1 : : 0/1 0/1 COM9 BIT1 0/1 0/1 : : 0/1 0/1 COM0 BIT0 0/1 0/1 : : 0/1 0/1 COM8 BIT0 0/1 0/1 : : 0/1 0/1
The LCDON instruction turns the LCD display on (even in HOLD mode), and the LCDOFF instruction turns the LCD display off. At the initial reset state, the LCD display is turned off automatically. To turn on the LCD display, the instruction LCDON must be executed.
5.25.1 LCD RAM addressing method There are 160 LCD RAMs (LCDR00H - LCDR4FH, LCDR80H - LCDR0CFH) that should be indirectly addressed. The LCD RAM pointer (LP) is used to point to the address of the wanted LCD RAM but it is not readable. The LP is organized as 8-bit binary register. The MOV LPL,R and MOV LPH,R instructions can load the LCD RAM address from RAM to the LP register. The MOV @LP,R and MOV R,@LP instructions can access the pointed LCD RAM content.
- 45 -
Publication Release Date: December 2000 Revision A1
W742E/C811
5.25.2 LCD voltage and contrast adjusting LCD power (VLCD2) has two source, one is directly from the VLCD1 pin, another is from internal pump circuit. The LCD power source is selected by mask option. The pump circuit doubles the C input voltage (VDD), the power consumption in internal pump mode is more than directly input from VLCD1. The LCD pump circuit only works in the VDD range from 2.4V to 4.0V. If the operating voltage of VDD is up 4.0V, the LCD power should come from the VLCD1 pin. The LCD contrast is adjustable by an internal variable resistor (VR). VLCD voltage is controlled by setting bit2, bit1 and bit0 of LCD contrast control register (LCDCC). LCDCC is determined by executing MOV LCDCC,#I. The Figure 518 shows the LDC power control as below:
outside chip VDD VLCD1 CP CN Internal Pump Circuit
EN
inside chip
S1 VLCD2 VR VLCD
R
V1
R
V2
R
V3
STOP LCDOFF Code Option
R
V4
R
VSS
Note: VR is determined by LCDCC register
Figure 5-18 LCD power control circuit
3 LCDCC
Note: W means write only.
2 W
1 W
0 W
LCDCC 0000H 0001H 0010H 0011H 0100H 0101H 0110H 0111H Bit 3 is reserved.
VLCD/VLCD2 1.00 0.96 0.93 0.89 0.86 0.81 0.76 0.71
- 46 -
W742E/C811
5.25.3 SEG32-SEG39 using as DC output (NMOS open drain type) SEG32-SEG39 pins output type can be changed to DC output mode by code mask option. The correspoinding control resigters are LCD RAM address LCDR40 and LCDR41, these two parts are individually enabled by code mask option. LCDR40 controls the SEG32-SEG35 pins and LCDR41 controls the SEG36- SEG39 pins. When SEG32-SEG39 are used as DC output, their output type is NMOS open drain type. The instruction MOV @LP,R outputs the ram data to SEG32-39, when SEG32-39 operate in DC output mode.
5.25.4 The output waveforms for the LCD driving mode 1/5 bias 1/8 (1/16) duty Lighting System (Example) Normal Operating Mode
1
2
3
4
"
"
"
8 (16)
1
2
3
4
"
"
"
8 (16)
COM0
"
"
"
"
"
"
VLCD V1 V2 V3 V4 VSS VLCD V1 V2 V3 V4 VSS VLCD V1 V2 V3 V4 VSS -V1 -V2 -V3 -V4 -VLCD
SEG
"
"
"
"
"
"
LCD driver outputs for seg. on COM0 side being lit
"
"
"
"
"
"
- 47 -
Publication Release Date: December 2000 Revision A1
W742E/C811
6. ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage to Ground Potential Applied Input/Output Voltage Power Dissipation Ambient Operating Temperature Storage Temperature
of the device.
RATING -0.3 to +7.0 -0.3 to +7.0 120 0 to +70 -55 to +150
UNIT V V mW C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
7. DC CHARACTERISTICS
(VDD-VSS = 3.0V, Fm = 3.58 MHz, Fs = 32.768 KHz, TA = 25 C, LCD on, INTERNAL PUMP DISABLE; unless otherwise specified)
PARAMETER OP. Voltage (W742C811) Op. Voltage (W742E811) Op. Current (Crystal type)
SYM. VDD VDD IOP1 IOP3
CONDITIONS No load (Ext-V) In dual-clock normal operatio
MIN. 2.4 2.4 -
TYP. 0.5
MAX. 5.5 4.8 1.0
UNIT V V mA A
Op. Current (Crystal type)
No load (Ext-V) In dual-clock slow operation and Fm is stopped
-
30
50
Hold Current (Crystal type)
IHM1
Hold mode No load (Ext-V) In dual-clock normal operation
-
400
500
A A
Hold Current (Crystal type)
IHM3
Hold mode No load (Ext-V) In dual-clock slow operation and Fm is stopped
-
30
50
Hold Current (Crystal type)
IHM5
Hold mode No load (Ext-V) VDD =5V; In dual-clock slow operation and Fm is stopped
-
50
80
A
Stop Current
ISM1 VIL VIH VML VMH
Stop mode No load (Ext-V) Fm and Fs are stopped
-
1
2
A V V V V
Input Low Voltage Input High Voltage MFP Output Low Voltage MFP Output High Voltage
IOL = 3.5 mA IOH = 3.5 mA
VSS 0.7 VDD 2.4
-
0.3 VDD VDD 0.4 -
- 48 -
W742E/C811
DC Characteristics, continued
PARAMETER Port RA, RB, RD Output Low Voltage Port RA, RB, RD Output High Voltage LCD Supply Current SEG0-SEG39 Sink Current (Used as LCD output) SEG0-SEG39 Drive Current (Used as LCD output) Port RE, RF Sink Current Port RE, RF Source Current DTMF Output DC Level DTMF Distortion DTMF Output Voltage Pre-emphasis Pull-up Resistor RES Pull-up Resistor
SYM. VABL VABH ILCD IOL1
CONDITIONS IOL = 2.0 mA IOH = 2.0 mA All Seg. ON VOL = 0.4V VLCD = 0.0V VOH = 2.4V VLCD = 3.0V VOL = 0.9V VOH = 2.4V RL = 5 K, VDD = 2.5 to 3.8V RL = 5 K, VDD = 2.5 to 3.8V Low group, RL = 5 K Col/Row
MIN. 2.4 90
TYP. -
MAX. 0.4 20 -
UNIT V V A A A mA mA V dB mVrms dB K K
IOH1
90
-
-
IEL IEH VTDC
THD
9 0.4 1.1 130 1 100 20
1.2 -30 150 2 350 100
2.8 -23 170 3 1000 500
VTO
RC RRES
Port RC
8. AC CHARACTERISTICS
PARAMETER Op. Frequency SYM. FOSC f f TI TRAW TIAW CONDITIONS RC type Crystal type Frequency Deviation by Voltage Drop for RC Oscillator Instruction Cycle Time Reset Active Width Interrupt Active Width f(3V) - f(2.4V) f(3V) One machine cycle FOSC = 32.768 KHz FOSC = 32.768 KHz 1 1 4/FOSC S S S MIN. TYP. 2000 3.58 MAX. 10 UNIT KHz MHz %
- 49 -
Publication Release Date: December 2000 Revision A1
W742E/C811
9. INSTRUCTION SET TABLE
Symbol Description ACC: ACC.n: WR: WRP: PAGE: DBKRL: DBKRH: ROMPR: MR0: MR1: PM0: PM1: PM4: PM5: PM6: PSR0: PSR1: PSR2: R: LP: LPL: LPH: R.n: I: L: CF: ZF: PC: Accumulator Accumulator bit n Working Register WR Page register Page Register Data Bank Register (Low nibble) Data Bank Register (High nibble) ROM Page Register Mode Register 0 Mode Register 1 Port Mode 0 Port Mode 1 Port Mode 4 Port Mode 5 Port Mode 6 Port Status Register 0 Port Status Register 1 Port Status Register 2 Memory (RAM) of address R LCD data RAM pointer Low nibble of the LCD data RAM pointer High nibble of the LCD data RAM pointer Memory bit n of address R Constant parameter Branch or jump address Carry Flag Zero Flag Program Counter
- 50 -
W742E/C811
Continued
TM0L: TM0H: TM1L: TM1H: LCDCC TAB0: TAB1: TAB2: TAB3: IEF.n: HCF.n: HEF.n: HEFD: SEF.n: PEF.n: P1EF.n: EVF.n: EVFD: ! =: &: ^: EX: : [PAGE*10H+()]: [P()]:
Low nibble of the Timer 0 counter High nibble of the Timer 0 counter Low nibble of the Timer 1 counter High nibble of the Timer 1 counter LCD contrast control register Look-up table address buffer 0 Look-up table address buffer 1 Look-up table address buffer 2 Look-up table address buffer 3 Interrupt Enable Flag n HOLD mode release Condition Flag n HOLD mode release Enable Flag n RD port HOLD mode release Enable Flag STOP mode wake-up Enable Flag n Port Enable Flag n P1 Port Enable Flag n Event Flag n RD port Event Flag n Not equal AND OR Exclusive OR Transfer direction, result Contents of address PAGE (bit2, bit1, bit0)*10H+() Contents of port P
- 51 -
Publication Release Date: December 2000 Revision A1
W742E/C811
MACHINE CODE Arithmetic 0001 1000 0xxx xxxx 0001 1100 i i i i nnnn 0001 1001 0xxx xxxx 0001 1101 i i i i nnnn 0000 1000 0xxx xxxx 0000 1100 i i i i nnnn 0000 1001 0xxx xxxx 0000 1101 i i i i nnnn 0010 1000 0xxx xxxx 0010 1100 i i i i nnnn 0010 1001 0xxx xxxx 0010 1101 i i i i nnnn 0001 1010 0xxx xxxx 0001 1110 i i i i nnnn 0001 1011 0xxx xxxx 0001 1111 i i i i nnnn 0000 1010 0xxx xxxx 0000 1110 i i i i nnnn 0000 1011 0xxxxxxx 0000 1111 i i i i nnnn 0100 1010 0xxx xxxx 0100 1010 1xxx xxxx ADD ADD
MNEMONIC
FUNCTION
FLAG AFFECTED
W/C
R, ACC WRn, #I R, ACC WRn, #I R, ACC WRn, #I R, ACC WRn, #I R, ACC WRn, #I R, ACC WRn, #I R, ACC WRn, #I R, ACC WRn, #I R, ACC WRn, #I R, ACC WRn, #I R R
ACC(R) + (ACC) ACC(WRn) + I ACC, R(R) + (ACC) ACC, WRn(WRn) + I ACC(R) + (ACC) + (CF) ACC(WRn) + I + (CF) ACC, R(R) + (ACC) + (CF) ACC, WRn(WRn) + I + (CF) ACC(R) + (ACC) ACC(WRn) + I ACC, R(R) + (ACC) ACC, WRn(WRn) + I ACC(R) - (ACC) ACC(WRn) - I ACC, R(R) - (ACC) ACC, WR(WR) - I ACC(R) - (ACC) - (CF) ACC(WRn) - I - (CF) ACC, R(R) - (ACC) - (CF) ACC, WRn(WRn) - I - (CF) ACC, R(R) + 1 ACC, R(R) - 1
ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF ZF ZF ZF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF
1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1
ADDR ADDR ADC ADC ADCR ADCR ADU ADU ADUR ADUR SUB SUB SUBR SUBR SBC SBC SBCR SBCR INC DEC
- 52 -
W742E/C811
Instruction set, continued MACHINE CODE Logic 0010 1010 0xxx xxxx 0010 1110 i i i i nnnn 0010 1011 0xxx xxxx 0010 1111 i i i i nnnn 0011 1010 0xxx xxxx 0011 1110 i i i i nnnn 0011 1011 0xxx xxxx 0011 1111 i i i i nnnn 0011 1000 0xxx xxxx 0011 1100 i i i i nnnn 0011 1001 0xxx xxxx 0011 1101 i i i i nnnn Branch 0111 0aaa aaaa aaaa 1000 0aaa aaaa aaaa 1001 0aaa aaaa aaaa 1010 0aaa aaaa aaaa 1011 0aaa aaaa aaaa 1110 0aaa aaaa aaaa 1100 0aaa aaaa aaaa 1111 0aaa aaaa aaaa 1101 0aaa aaaa aaaa 0100 1000 0xxx xxxx 0100 1000 1xxx xxxx 1010 1000 0xxx xxxx 1010 1000 1xxx xxxx 1010 1001 0xxx xxxx 1010 1001 1xxx xxxx JMP JB0 JB1 JB2 JB3 JZ JNZ JC JNC DSKZ DSKNZ SKB0 SKB1 SKB2 SKB3 L L L L L L L L L R R R R R R PC13~PC0(ROMPR)x800H+L10~L0 PC10~PC0L10~L0; if ACC.0 = "1" PC10~PC0L10~L0; if ACC.1 = "1" PC10~PC0L10~L0; if ACC.2 = "1" PC10~PC0L10~L0; if ACC.3 = "1" PC10~PC0L10~L0; if ACC = 0 PC10~PC0L10~L0; if ACC ! = 0 PC10~PC0L10~L0; if CF = "1" PC10~PC0L10~L0; if CF ! = "1" ACC, R(R) - 1; PC (PC) + 2 if ACC = 0 ACC, R(R) - 1; PC (PC) + 2 if ACC ! = 0 PC (PC) + 2 if R.0 = "1" PC (PC) + 2 if R.1 = "1" PC (PC) + 2 if R.2 = "1" PC (PC) + 2 if R.3 = "1" ZF, CF ZF, CF 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 ANL ANL ANLR ANLR ORL ORL ORLR ORLR XRL XRL XRLR XRLR R, ACC WRn, #I R, ACC WRn, #I R, ACC WRn, #I R, ACC WRn, #I R, ACC WRn, #I R, ACC WRn, #I ACC(R) & (ACC) ACC(WRn) & I ACC, R(R) & (ACC) ACC, WRn(WRn) & I ACC(R) (ACC) ACC(WRn) I ACC, R(R) (ACC) ACC, WRn(WRn) I ACC(R) EX (ACC) ACC(WRn) EX I ACC, R(R) EX (ACC) ACC, WRn(WRn) EX I ZF ZF ZF ZF ZF ZF ZF ZF ZF ZF ZF ZF 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 MNEMONIC FUNCTION FLAG AFFECTED W/C
- 53 -
Publication Release Date: December 2000 Revision A1
W742E/C811
Instruction set, continued MACHINE CODE Subroutine 0110 0aaa aaaa aaaa CALL L STACK (PC)+1, TAB0, TAB1, TAB2, TAB3, DBKRL,DBKRH,WRP,ROMPR,PAGE,ACC,CF PC13 ~ PC0 (ROMPR)x800H+L10 ~ L0 0000 0001 0000 0000 0000 0001 I I I I I I I I RTN RTN #I Pop PC Pop PC; Pop other registers by I setting refer to below table 1/1 1/1 1/1 MNEMONIC FUNCTION FLAG AFFECTED W/C
Bit definition of I I = 0000 0000 bit0 = 1 bit1 = 1 bit2 = 1 bit3 = 1 bit4 = 1 bit5 = 1 bit6 = 1 Pop PC from stack only Pop TAB0, TAB1, TAB2, TAB3 from stack Pop DBKRL, DBKRH from stack Pop WRP from stack Pop ROMPR from stack Pop PAGE from stack Pop ACC from stack Pop CF from stack
- 54 -
W742E/C811
Instruction set, continued INSTRUCTION SET Data move 1110 1nnn nxxx xxxx 1111 1nnn nxxx xxxx 0110 1nnn nxxx xxxx 0111 1nnn nxxx xxxx 0101 1001 1xxx xxxx 0100 1110 1xxx xxxx 1011 1 i i i i xxx xxxx 1100 1nnn n000 qqqq 1101 1nnn n000 qqqq 1000 1100 0xxx xxxx 1000 1100 1xxx xxxx 1000 1110 0xxx xxxx 1000 1110 1xxx xxxx 1000 1101 0xxx xxxx Input & Output 0101 1011 0xxx xxxx 0101 1011 1xxx xxxx 0100 1011 0xxx xxxx 0100 1011 1xxx xxxx 0101 1100 0xxx xxxx 0101 1100 0xxx xxxx 0101 1010 0xxx xxxx 0101 1010 1xxx xxxx 1010 1100 0xxx xxxx 1010 1100 1xxx xxxx 0101 1110 0xxx xxxx 1010 1110 0xxx xxxx 1010 1101 0xxx xxxx 0001 0010 i i i i i i i i MOVA MOVA MOVA MOVA MOVA MOVA MOV MOV MOV MOV MOV MOV MOV MOV R, RA R, RB R, RC R, RD R, P0 R, P1 RA, R RB, R RC, R RD, R RE, R RF, R P0, R MFP, #I ACC, R[RA] ACC, R[RB] ACC, R[RC] ACC, R[RD] ACC, R[P0] ACC, R[P1] [RA](R) [RB](R) [RC](R) [RD](R) [RE](R) [RF](R) [P0](R) [MFP] I ZF ZF ZF ZF ZF ZF 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 MOV MOV MOVA MOVA MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVC WRn, R R, WRn WRn, R R, WRn R, ACC ACC, R R, #I WRn, @WRq @WRq, WRn TAB0, R TAB1, R TAB2, R TAB3, R R WRn(R) R(WRn) ACC, WRn(R) ACC, R(WRn) R(ACC) ACC(R) RI WRn[(DBKRH)x800H+(DBKRL)x8 0H+(PAGE)x10H +(WRq)] [(DBKRH)x800H+(DBKRL)x80H+(PA GE)x10H +(WRq)]WRn TAB0(R) TAB1(R) TAB2(R) TAB3(R) R[(TAB3)x1000H+(TAB2)x100H+ (TAB1) x10H + (TAB0)]/4 ZF ZF ZF 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/2 1/2 1/1 1/1 1/1 1/1 1/2 CONTINUED INSTRUCTION SET FLAG AFFECTED W/C
- 55 -
Publication Release Date: December 2000 Revision A1
W742E/C811
Instruction set, continued MACHINE CODE Flag & Register 0101 1111 1xxx xxxx 0101 1110 1xxx xxxx 0101 0110 1000 0i i i 1001 1101 1xxx xxxx 1001 1100 1xxx xxxx 0011 0101 1000 i i i i 0011 0101 0000 i i i i 0011 0101 0100 000 i 1001 1101 0000nnnn 1001 1101 0100nnnn 1001 1100 0000nnnn 1001 1100 0100nnnn 0011 0100 0000 0 i i i 1000 1000 0xxx xxxx 1000 1001 0xxx xxxx 0001 0011 1000 i 0 0 i 0001 0011 0000 i i i i 0101 1001 0xxx xxxx 0101 1000 0xxx xxxx 0100 1001 0xxx xxxx 0100 1001 1xxx xxxx 0101 0011 0000 i i i i 0101 0111 0000 i i i i 0101 0111 1000 i i i i 0011 0111 0000 i i i i 0011 0111 1000 i i i i 0101 0011 1000 i i i i 0100 0000 i 0 0 i i i i i 0011 0000 0000 0000 MOVA MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVA MOV MOVA MOVA MOV MOV MOV MOV MOV MOV CLR CLR R, PAGE PAGE, R PAGE, #I R, WRP WRP, R WRP, #I DBKRL, #I DBKRH, #I WRn,DBKRL WRn,DBKRH DBKRL, WRn DBKRH, WRn ROMPR, #I ROMPR, R R, ROMPR MR0, #I MR1, #I R, CF CF, R R, HCFL R, HCFH PM0, #I PM1, #I PM2, #I PM4, #I PM5, #I PM6, #I EVF, #I EVFD ACC, RPAGE (Page Register) PAGE(R) PAGEI RWRP WRP(R) WRPI DBKRLI DBKRHI WRnDBKRL WRnDBKRH DBKRLWRn DBKRHWRn ROMPRI ROMPR(R) R(ROMPR) MR0I MR1I ACC.0, R.0CF CF(R.0) ACC, RHCF.0~HCF.3 ACC, RHCF.4~HCF.7 Port Mode 0 I Port Mode 1 I Port Mode 2 I Port Mode 4 I Port Mode 5 I Port Mode 6 I Clear Event Flag if In = 1 Clear RD Event Flag if In = 1 ZF CF ZF ZF ZF 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 MNEMONIC FUNCTION FLAG AFFECTED W/C
- 56 -
W742E/C811
Instruction set, continued MACHINE CODE Flag & Register 0101 1101 0xxx xxxx 0101 1101 1xxx xxxx 0100 0001 i i i i i i i i 0011 0001 0000 000 i 0101 0001 i i i i i i i i 0100 0011 0000 i i i i 0011 0011 0000 i i 00 0101 0010 i i i i i i i i 0101 0100 0000 i i i i 0100 1111 0xxx xxxx 0100 1111 1xxx xxxx 0101 1111 0xxx xxxx 0100 0010 0000 0000 0100 0010 1000 0000 0100 0010 1100 0000 0101 0000 0100 0000 0101 0000 0000 0000 0001 0111 0000 0000 0101 0101 1000 0000 0001 0111 1000 0000 Shift & Rotate 0100 1101 0xxx xxxx SHRC R ACC.n, R.n(R.n+1); ACC.3, R.30; CFR.0 0100 1101 1xxx xxxx RRC R ACC.n, R.n(R.n+1); ACC.3, R.3CF; CFR.0 0100 1100 0xxx xxxx SHLC R ACC.n, R.n(R.n-1); ACC.0, R.00; CFR.3 0100 1100 1xxx xxxx RLC R ACC.n, R.n(R.n-1); ACC.0, R.0CF; CFR.3 ZF, CF 1/1 ZF, CF 1/1 ZF, CF 1/1 ZF, CF 1/1 MOVA MOVA MOV MOV MOV MOV MOV MOV MOV MOVA MOVA MOVA CLR CLR CLR SET CLR CLR CLR CLR R, EVFL R, EVFH HEF, #I HEFD,#I IEF, #I PEF, #I P1EF, #I SEF, #I SCR, #I R, PSR0 R, PSR1 R, PSR2 PSR0 PSR1 PSR2 CF CF DIVR0 DIVR1 WDT ACC, R EVF.0 - EVF.3 ACC, R EVF.4 - EVF.7 Set/Reset HOLD mode release Enable Flag Set/Reset RD HOLD mode release Enable Flag Set/Reset Interrupt Enable Flag Set/Reset Port Enable Flag Set/Reset P1 Port Enable Flag Set/Reset STOP mode wake-up Enable Flag for RC,RD port SCRI ACC, RPort Status Register 0 ACC, RPort Status Register 1 ACC, RPort Status Register 2 Clear Port Status Register 0 Clear Port Status Register 1 Clear Port Status Register 2 Set Carry Flag Clear Carry Flag Clear the last 4-bit of the Divider 0 Clear the last 4-bit of the Divider 1 Clear WatchDog Timer CF CF ZF ZF ZF ZF ZF 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 MNEMONIC FUNCTION FLAG AFFECTED W/C
- 57 -
Publication Release Date: December 2000 Revision A1
W742E/C811
Instruction set, continued MACHINE CODE LCD 1001 1000 0xxx xxxx 1001 1000 1xxx xxxx 1001 1010 0xxx xxxx 1001 1011 0xxx xxxx 0000 0010 0000 0000 0000 0010 1000 0000 0000 0011 0000 0 i i i Serial I/O 0011 0010 0000 i i i i 1010 1111 0xxx xxxx 1001 1111 0xxx xxxx DTMF 0011 0100 1000 i i i i 1001 1110 1xxx xxxx Timer 1010 1010 0xxx xxxx 1010 1010 1xxx xxxx 1010 1011 0xxx xxxx 1010 1011 1xxx xxxx 1000 1111 0xxx xxxx 1000 1111 1xxx xxxx 1001 1001 0xxx xxxx 1001 1001 1xxx xxxx Other 0000 0000 1000 0000 0000 0000 1100 0000 0000 0000 0000 0000 0101 0000 1100 0000 0101 0000 1000 0000 HOLD STOP NOP EN DIS INT INT Enter Hold mode Enter Stop mode No operation Enable interrupt function Disable interrupt function 1/1 1/1 1/1 1/1 1/1 MOV MOV MOV MOV MOV MOV MOV MOV TM0L, R TM0H, R TM1L, R TM1H, R R, TM0L R, TM0H R, TM1L R, TM1H TM0L(R) TM0H(R) TM1L(R) TM1H(R) (R)TM0L (R)TM0H (R)TM1L (R)TM1H 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 MOV MOV DTCR, #I DTMF, R DTMF Enable Control Select DTMF frequency 1/1 1/1 MOV SOP SIP SIC, #I R R Serial Interface Control P0.1R(high nibble),A(low nibble) Serially R(high nibble), A(low nibble) P0.1 Serially ZF 1/1 1/1 1/1 MOV MOV MOV MOV LCDON LCDOFF MOV LCDCC, #I LPL, R LPH, R @LP, R R, @LP LPL(R) LPH(R) [(LPH)x10H+(LPL)](R) R[(LPH) x10H+(LPL)] LCD ON LCD OFF LCD contrast control 1/1 1/1 1/1 1/1 1/1 1/1 1/1 MNEMO NIC FUNCTION FLAG AFFECTED W/C
- 58 -
W742E/C811
10. PACKAGE DIMENSIONS
100L QFP (14 x 20 x 2.75 mm footprint 4.8 mm)
HD D
E
HE
e
b
c
A2 A See Detail F Seating Plane y A1 L L
1
Controlling dimension: Millimeters
Symbol
Dimension in inch
Dimension in mm
Min. N o m .
Max.
Min. N o m . Max.
A A1 A2 b c D E e HD HE L L1 y
0.010 0.014 0.101 0.008 0.004 0.547 0.783 0.020 0.728 0.960 0.039 0.107 0.012 0.006 0.551 0.787 0.026 0.740 0.976 0.047 0.064
0.018 0.113 0.016 0.008 0.555 0.791 0.032 0.756 0.992 0.055
0.25 2.57 0.20 0.10 13.90 19.90 0.498 18.40 24.40 1.00
0.35 2.72 0.30 0.15 14.00 20.00 0.65 18.80 24.80 1.20 2.40
0.45 2.87 0.40 0.20 14.10 20.10 0.802 19.20 25.20 1.40
0.003 0 7 0
0.08 7
- 59 -
Publication Release Date: December 2000 Revision A1
W742E/C811
Headquarters
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 4, Creation Rd. III, No. 378 Kwun Tong Rd; Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852 -27513100 TEL: 886-3-5770066 FAX: 852 -27552064 FAX: 886 -3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886 -2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min -Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886 -2-27197502
Note: All data and specifications are subject to change withou t notice.
- 60 -

▲Up To Search▲

Price & Availability of W742E

	To Download W742E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .